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Reorganized the configs.

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This commit is contained in:
Ross Thompson 2022-10-09 16:46:48 -05:00
parent 382ccf74a5
commit b52f593ecb
5 changed files with 25 additions and 25 deletions
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18
pipelined/config/rv32i/wally-config.vh
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@ -38,11 +38,11 @@
`define IEEE754 0 `define IEEE754 0
// I // I
`define MISA (32'h00000100 | 1 << 20 | 1 << 18 ) `define MISA (32'h00000104)
`define ZICSR_SUPPORTED 1 `define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 0
`define COUNTERS 32 `define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 0
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features // Microarchitectural Features
@ -50,11 +50,11 @@
`define UARCH_SUPERSCALR 0 `define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0 `define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 1 `define BUS 0
`define DCACHE 0 `define DCACHE 0
`define ICACHE 0 `define ICACHE 0
`define VIRTMEM_SUPPORTED 0 `define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
`define BIGENDIAN_SUPPORTED 0 `define BIGENDIAN_SUPPORTED 0
// TLB configuration. Entries should be a power of 2 // TLB configuration. Entries should be a power of 2
@ -101,16 +101,16 @@
`define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_BASE 34'h80000000
`define EXT_MEM_RANGE 34'h07FFFFFF `define EXT_MEM_RANGE 34'h07FFFFFF
`define CLINT_SUPPORTED 1'b1 `define CLINT_SUPPORTED 1'b0
`define CLINT_BASE 34'h02000000 `define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF `define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b1 `define GPIO_SUPPORTED 1'b0
`define GPIO_BASE 34'h10060000 `define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF `define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b1 `define UART_SUPPORTED 1'b0
`define UART_BASE 34'h10000000 `define UART_BASE 34'h10000000
`define UART_RANGE 34'h00000007 `define UART_RANGE 34'h00000007
`define PLIC_SUPPORTED 1'b1 `define PLIC_SUPPORTED 1'b0
`define PLIC_BASE 34'h0C000000 `define PLIC_BASE 34'h0C000000
`define PLIC_RANGE 34'h03FFFFFF `define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b0 `define SDC_SUPPORTED 1'b0

14
pipelined/config/rv32ic/wally-config.vh
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@ -37,11 +37,11 @@
// IEEE 754 compliance // IEEE 754 compliance
`define IEEE754 0 `define IEEE754 0
`define MISA (32'h00000104) `define MISA (32'h00000104 | 1 << 20 | 1 << 18 )
`define ZICSR_SUPPORTED 1 `define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 0 `define ZIFENCEI_SUPPORTED 1
`define COUNTERS 32 `define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 0 `define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features // Microarchitectural Features
@ -49,7 +49,7 @@
`define UARCH_SUPERSCALR 0 `define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0 `define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 0 `define BUS 1
`define DCACHE 0 `define DCACHE 0
`define ICACHE 0 `define ICACHE 0
`define VIRTMEM_SUPPORTED 0 `define VIRTMEM_SUPPORTED 0
@ -103,13 +103,13 @@
`define CLINT_SUPPORTED 1'b1 `define CLINT_SUPPORTED 1'b1
`define CLINT_BASE 34'h02000000 `define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF `define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b0 `define GPIO_SUPPORTED 1'b1
`define GPIO_BASE 34'h10060000 `define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF `define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b0 `define UART_SUPPORTED 1'b1
`define UART_BASE 34'h10000000 `define UART_BASE 34'h10000000
`define UART_RANGE 34'h00000007 `define UART_RANGE 34'h00000007
`define PLIC_SUPPORTED 1'b0 `define PLIC_SUPPORTED 1'b1
`define PLIC_BASE 34'h0C000000 `define PLIC_BASE 34'h0C000000
`define PLIC_RANGE 34'h03FFFFFF `define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b0 `define SDC_SUPPORTED 1'b0

6
pipelined/config/rv64i/wally-config.vh
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@ -38,11 +38,11 @@
`define IEEE754 0 `define IEEE754 0
// MISA RISC-V configuration per specification I // MISA RISC-V configuration per specification I
`define MISA (32'h00000100 | 1 << 20 | 1 << 18 ) `define MISA (32'h00000104 )
`define ZICSR_SUPPORTED 1 `define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 0
`define COUNTERS 32 `define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 1 `define ZICOUNTERS_SUPPORTED 0
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
/// Microarchitectural Features /// Microarchitectural Features

8
pipelined/config/rv64ic/wally-config.vh
View File

@ -38,11 +38,11 @@
`define IEEE754 0 `define IEEE754 0
// MISA RISC-V configuration per specification // MISA RISC-V configuration per specification
`define MISA (32'h00000104) `define MISA (32'h00000104 | 1 << 20 | 1 << 18 )
`define ZICSR_SUPPORTED 1 `define ZICSR_SUPPORTED 1
`define ZIFENCEI_SUPPORTED 0 `define ZIFENCEI_SUPPORTED 1
`define COUNTERS 32 `define COUNTERS 32
`define ZICOUNTERS_SUPPORTED 0 `define ZICOUNTERS_SUPPORTED 1
`define ZFH_SUPPORTED 0 `define ZFH_SUPPORTED 0
// Microarchitectural Features // Microarchitectural Features
@ -51,7 +51,7 @@
`define UARCH_SINGLECYCLE 0 `define UARCH_SINGLECYCLE 0
// LSU microarchitectural Features // LSU microarchitectural Features
`define BUS 0 `define BUS 1
`define DCACHE 0 `define DCACHE 0
`define ICACHE 0 `define ICACHE 0
`define VIRTMEM_SUPPORTED 0 `define VIRTMEM_SUPPORTED 0

4
pipelined/regression/regression-wally
View File

@ -82,7 +82,7 @@ for test in tests32gc:
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c"] tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c", "wally32periph"]
for test in tests32ic: for test in tests32ic:
tc = TestCase( tc = TestCase(
name=test, name=test,
@ -91,7 +91,7 @@ for test in tests32ic:
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
tests32i = ["arch32i", "wally32periph"] tests32i = ["arch32i", "imperas32i"]
for test in tests32i: for test in tests32i:
tc = TestCase( tc = TestCase(
name=test, name=test,