From b52f593ecb1b5d5aa59aefb215acc766871586fa Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 9 Oct 2022 16:46:48 -0500 Subject: [PATCH] Reorganized the configs. --- pipelined/config/rv32i/wally-config.vh | 18 +++++++++--------- pipelined/config/rv32ic/wally-config.vh | 14 +++++++------- pipelined/config/rv64i/wally-config.vh | 6 +++--- pipelined/config/rv64ic/wally-config.vh | 8 ++++---- pipelined/regression/regression-wally | 4 ++-- 5 files changed, 25 insertions(+), 25 deletions(-) diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 09c14606..3d89efac 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -38,11 +38,11 @@ `define IEEE754 0 // I -`define MISA (32'h00000100 | 1 << 20 | 1 << 18 ) +`define MISA (32'h00000104) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 +`define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 +`define ZICOUNTERS_SUPPORTED 0 `define ZFH_SUPPORTED 0 // Microarchitectural Features @@ -50,11 +50,11 @@ `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features -`define BUS 1 +`define BUS 0 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 // TLB configuration. Entries should be a power of 2 @@ -101,16 +101,16 @@ `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 +`define CLINT_SUPPORTED 1'b0 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 +`define GPIO_SUPPORTED 1'b0 `define GPIO_BASE 34'h10060000 `define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 +`define UART_SUPPORTED 1'b0 `define UART_BASE 34'h10000000 `define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 +`define PLIC_SUPPORTED 1'b0 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF `define SDC_SUPPORTED 1'b0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index d865623d..ba47915d 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -37,11 +37,11 @@ // IEEE 754 compliance `define IEEE754 0 -`define MISA (32'h00000104) +`define MISA (32'h00000104 | 1 << 20 | 1 << 18 ) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 0 +`define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 +`define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 // Microarchitectural Features @@ -49,7 +49,7 @@ `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features -`define BUS 0 +`define BUS 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 @@ -103,13 +103,13 @@ `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b0 +`define GPIO_SUPPORTED 1'b1 `define GPIO_BASE 34'h10060000 `define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b0 +`define UART_SUPPORTED 1'b1 `define UART_BASE 34'h10000000 `define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b0 +`define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF `define SDC_SUPPORTED 1'b0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 05af9011..252e5482 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -38,11 +38,11 @@ `define IEEE754 0 // MISA RISC-V configuration per specification I -`define MISA (32'h00000100 | 1 << 20 | 1 << 18 ) +`define MISA (32'h00000104 ) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 +`define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 +`define ZICOUNTERS_SUPPORTED 0 `define ZFH_SUPPORTED 0 /// Microarchitectural Features diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index e820e57c..0afe314b 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -38,11 +38,11 @@ `define IEEE754 0 // MISA RISC-V configuration per specification -`define MISA (32'h00000104) +`define MISA (32'h00000104 | 1 << 20 | 1 << 18 ) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 0 +`define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 +`define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 // Microarchitectural Features @@ -51,7 +51,7 @@ `define UARCH_SINGLECYCLE 0 // LSU microarchitectural Features -`define BUS 0 +`define BUS 1 `define DCACHE 0 `define ICACHE 0 `define VIRTMEM_SUPPORTED 0 diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 48dd7c26..15c7a0a2 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -82,7 +82,7 @@ for test in tests32gc: grepstr="All tests ran without failures") configs.append(tc) -tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c"] +tests32ic = ["arch32i", "arch32c", "imperas32i", "imperas32c", "wally32periph"] for test in tests32ic: tc = TestCase( name=test, @@ -91,7 +91,7 @@ for test in tests32ic: grepstr="All tests ran without failures") configs.append(tc) -tests32i = ["arch32i", "wally32periph"] +tests32i = ["arch32i", "imperas32i"] for test in tests32i: tc = TestCase( name=test,