diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 80edad36..09257c18 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/DataStall -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/DataStall +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -209,35 +209,38 @@ add wave -noupdate -group icache -expand -group memory -group {tag write} /testb add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/BusState -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/ProposedNextBusState -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/NextBusState -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/ISquashBusAccessF -add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM -add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM -add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM -add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HCLK -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRESETn -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRDATA -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HREADY -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRESP -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDR -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWDATA -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITE -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZE -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HBURST -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HPROT -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HTRANS -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HMASTLOCK -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDRD -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED -add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED +add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState +add wave -noupdate -group AHB /testbench/dut/hart/ebu/ProposedNextBusState +add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState +add wave -noupdate -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM +add wave -noupdate -group AHB /testbench/dut/hart/ebu/ISquashBusAccessF +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemReadM +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemWriteM +add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED +add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu /testbench/dut/hart/arbiter/MemAdrM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/AtomicMaskedM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -280,7 +283,7 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {14425 ns} 0} +WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {10763646 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 189 @@ -296,4 +299,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {2330991 ns} +WaveRestoreZoom {10763302 ns} {10763880 ns} diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 0ab4022c..8063ae48 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -100,13 +100,14 @@ module lsu ( logic SquashSCM; logic DTLBPageFaultM; logic MemAccessM; - logic [1:0] CurrState, NextState; + logic [2:0] CurrState, NextState; logic preCommittedM; localparam STATE_READY = 0; localparam STATE_FETCH = 1; - localparam STATE_FETCH_AMO = 2; - localparam STATE_STALLED = 3; + localparam STATE_FETCH_AMO_1 = 2; + localparam STATE_FETCH_AMO_2 = 3; + localparam STATE_STALLED = 4; logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. @@ -195,31 +196,70 @@ module lsu ( endgenerate // Data stall - assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO); + //assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2); // Ross Thompson April 22, 2021 // for now we need to handle the issue where the data memory interface repeately // requests data from memory rather than issuing a single request. - flopr #(2) stateReg(.clk(clk), + flopr #(3) stateReg(.clk(clk), .reset(reset), .d(NextState), .q(CurrState)); always_comb begin case (CurrState) - STATE_READY: if (|AtomicMaskedM) NextState = STATE_FETCH_AMO; // *** should be some misalign check - else if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH; - else NextState = STATE_READY; - STATE_FETCH_AMO: if (MemAckW) NextState = STATE_FETCH; - else NextState = STATE_FETCH_AMO; - STATE_FETCH: if (MemAckW & ~StallW) NextState = STATE_READY; // StallW will stay high if datastall stays high, so right now, once we get into STATE_FETCH, datastall goes high, and we never leave - else if (MemAckW & StallW) NextState = STATE_STALLED; - else NextState = STATE_FETCH; - STATE_STALLED: if (~StallW) NextState = STATE_READY; - else NextState = STATE_STALLED; - default: NextState = STATE_READY; + STATE_READY: + if (|AtomicMaskedM) begin + NextState = STATE_FETCH_AMO_1; // *** should be some misalign check + DataStall = 1'b1; + end else if (MemAccessM & ~DataMisalignedM) begin + NextState = STATE_FETCH; + DataStall = 1'b1; + end else begin + NextState = STATE_READY; + DataStall = 1'b0; + end + STATE_FETCH_AMO_1: + DataStall = 1'b1; + if (MemAckW) begin + NextState = STATE_FETCH_AMO_2; + end else begin + NextState = STATE_FETCH_AMO_1; + end + STATE_FETCH_AMO_2: begin + DataStall = 1'b1; + if (MemAckW & ~StallW) begin + NextState = STATE_FETCH_AMO_2; + end else if (MemAckW & StallW) begin + NextState = STATE_STALLED; + end else begin + NextState = STATE_FETCH_AMO_2; + end + end + STATE_FETCH: begin + DataStall = 1'b1; + if (MemAckW & ~StallW) begin + NextState = STATE_READY; + end else if (MemAckW & StallW) begin + NextState = STATE_STALLED; + end else begin + NextState = STATE_FETCH; + end + end + STATE_STALLED: begin + DataStall = 1'b0; + if (~StallW) begin + NextState = STATE_READY; + end else begin + NextState = STATE_STALLED; + end + end + default: begin + DataStall = 1'b0; + NextState = STATE_READY; + end endcase end