Gave names to for loops in generate blocks for ease of reference

wally-pipelined/src/cache/ICacheCntrl.sv

@@ -425,8 +425,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
   // store read data from memory interface before writing into SRAM.
   genvar 				i;
   generate
-    for (i = 0; i < WORDSPERLINE; i++) begin
-      flopenr #(`XLEN) flop(.clk(clk),
+    for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer
+      flopenr #(`XLEN) sb(.clk(clk),
 			    .reset(reset), 
 			    .en(InstrAckF & (i == FetchCount)),
 			    .d(InstrInF),

wally-pipelined/src/cache/dmapped.sv

@@ -106,7 +106,7 @@ module rodirectmappedmem #(parameter NUMLINES=512, parameter LINESIZE = 256, par
     assign DataWord = ReadLineTransformed[ReadOffset];
     genvar i;
     generate
-        for (i=0; i < LINESIZE/WORDSIZE; i++) begin
+        for (i=0; i < LINESIZE/WORDSIZE; i++) begin:readline
             assign ReadLineTransformed[i] = ReadLine[(i+1)*WORDSIZE-1:i*WORDSIZE];
         end
     endgenerate
@@ -214,7 +214,7 @@ module wtdirectmappedmem #(parameter NUMLINES=512, parameter LINESIZE = 256, par
     assign DataWord = ReadLineTransformed[ReadOffset];
     genvar i;
     generate
-        for (i=0; i < LINESIZE/WORDSIZE; i++) begin
+        for (i=0; i < LINESIZE/WORDSIZE; i++) begin:readline
             assign ReadLineTransformed[i] = ReadLine[(i+1)*WORDSIZE-1:i*WORDSIZE];
         end
     endgenerate

wally-pipelined/src/generic/shift.sv

@@ -38,8 +38,7 @@ module shift_right #(parameter WIDTH=8)
 
    assign stage[0] = A;   
    generate
-      for (i=0;i<$clog2(WIDTH);i=i+1)
-	begin : genbit
+      for (i=0;i<$clog2(WIDTH);i=i+1) begin : genbit
 	      mux2 #(WIDTH) mux_inst (stage[i], 
 				   {{(WIDTH/(2**(i+1))){1'b0}}, stage[i][WIDTH-1:WIDTH/(2**(i+1))]}, 
 				   Shift[$clog2(WIDTH)-i-1], 
@@ -60,8 +59,7 @@ module shift_left #(parameter WIDTH=8)
    
    assign stage[0] = A;   
    generate
-      for (i=0;i<$clog2(WIDTH);i=i+1)
-	begin : genbit
+      for (i=0;i<$clog2(WIDTH);i=i+1) begin : genbit
 	     mux2 #(WIDTH) mux_inst (stage[i], 
 				   {stage[i][WIDTH-1-WIDTH/(2**(i+1)):0], {(WIDTH/(2**(i+1))){1'b0}}}, 
 				   Shift[$clog2(WIDTH)-i-1], 

wally-pipelined/src/ifu/SRAM2P1R1W.sv

@@ -97,7 +97,7 @@ module SRAM2P1R1W
   
   // write port
   generate
-    for (index = 0; index < Width; index = index + 1) begin    
+    for (index = 0; index < Width; index = index + 1) begin:mem
       always_ff @ (posedge clk) begin
 	      if (WEN1Q & BitWEN1[index]) begin
 	        memory[WA1Q][index] <= WD1Q[index];

wally-pipelined/src/ifu/localHistoryPredictor.sv

@@ -67,7 +67,7 @@ module localHistoryPredictor
 
   genvar 		   index;
   generate
-    for (index = 0; index < 2**m; index = index +1) begin
+    for (index = 0; index < 2**m; index = index +1) begin:localhist
       
       flopenr #(k) LocalHistoryRegister(.clk(clk),
 					.reset(reset),

wally-pipelined/src/lsu/dcache.sv

@@ -151,7 +151,7 @@ module dcachecontroller #(parameter LINESIZE = 256) (
 
     genvar i;
     generate
-        for (i=0; i < WORDSPERLINE; i++) begin
+        for (i=0; i < WORDSPERLINE; i++) begin:sb
             flopenr #(`XLEN) flop(clk, reset, FetchState & (i == FetchWordNum), ReadDataW, DCacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]);
         end
     endgenerate

wally-pipelined/src/lsu/lsuArb.sv

@@ -138,12 +138,14 @@ module lsuArb
   assign MemRWMtoLSU = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
   
   generate
-    if (`XLEN == 32) begin
+    assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
+  /*  if (`XLEN == 32) begin
       assign Funct3MtoLSU = SelPTW ? 3'b010 : Funct3M;
     end else begin
       assign Funct3MtoLSU = SelPTW ? 3'b011 : Funct3M;
-    end
+    end*/
   endgenerate
+  mux2 sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoLSU);
 
   assign AtomicMtoLSU = SelPTW ? 2'b00 : AtomicM;
   assign MemAdrMtoLSU = SelPTW ? HPTWPAdr : MemAdrM;

wally-pipelined/src/mmu/pmpadrdec.sv

@@ -76,8 +76,9 @@ module pmpadrdec (
   generate
     assign Mask[1:0] = 2'b11;
     assign Mask[2] = (AdrMode == NAPOT); // mask has 0s in upper bis for NA4 region
-    for (i=3; i < `PA_BITS; i=i+1) 
+    for (i=3; i < `PA_BITS; i=i+1) begin:mask
       assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore
+    end
    endgenerate
   // verilator lint_on UNOPTFLAT
 

wally-pipelined/src/mmu/pmpchecker.sv

@@ -63,12 +63,6 @@ module pmpchecker (
   // verilator lint_on UNOPTFLAT
   logic [`PMP_ENTRIES-1:0]   PAgePMPAdr;  // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
   genvar i,j;
- /*
-  generate // extract 8-bit chunks from PMPCFG array
-    for (j=0; j<`PMP_ENTRIES; j = j+8)
-      assign {PMPCfg[j+7], PMPCfg[j+6], PMPCfg[j+5], PMPCfg[j+4],
-              PMPCfg[j+3], PMPCfg[j+2], PMPCfg[j+1], PMPCfg[j]} = PMPCFG_ARRAY_REGW[j/8];
-  endgenerate */
 
   pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
     .PhysicalAddress, 
@@ -80,7 +74,6 @@ module pmpchecker (
     .NoLowerMatchOut(NoLowerMatch),
     .Match, .Active, .L, .X, .W, .R);
 
-
   // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
   assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; 
 

wally-pipelined/src/mmu/tlbpriority.sv

@@ -41,8 +41,9 @@ module tlbpriority #(parameter ENTRIES = 8) (
   genvar i;
   generate
     assign nolower[0] = 1;
-    for (i=1; i<ENTRIES; i++) 
+    for (i=1; i<ENTRIES; i++) begin:therm
       assign nolower[i] = nolower[i-1] & ~a[i-1];
+    end
   endgenerate
   // verilator lint_on UNOPTFLAT
   assign y = a & nolower;

wally-pipelined/src/muldiv/div.sv

@@ -299,8 +299,7 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c,
    logic [WIDTH:0] 					  carry_temp;   
    genvar 						  i;
    generate
-      for (i=0;i<WIDTH;i=i+1)
-	begin : genbit
+      for (i=0;i<WIDTH;i=i+1) begin : genbit
 	    fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
 	  end
    endgenerate

wally-pipelined/src/uncore/uartPC16550D.sv

@@ -291,7 +291,7 @@ module uartPC16550D(
   // although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop
   generate
     genvar i;
-    for (i=0; i<16; i++) begin
+    for (i=0; i<16; i++) begin:rx
       assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
       if (i > 0)
         assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);