diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index 748b3f5e..6c1981ee 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -425,8 +425,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) // store read data from memory interface before writing into SRAM. genvar i; generate - for (i = 0; i < WORDSPERLINE; i++) begin - flopenr #(`XLEN) flop(.clk(clk), + for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer + flopenr #(`XLEN) sb(.clk(clk), .reset(reset), .en(InstrAckF & (i == FetchCount)), .d(InstrInF), diff --git a/wally-pipelined/src/cache/dmapped.sv b/wally-pipelined/src/cache/dmapped.sv index f40da412..42669752 100644 --- a/wally-pipelined/src/cache/dmapped.sv +++ b/wally-pipelined/src/cache/dmapped.sv @@ -106,7 +106,7 @@ module rodirectmappedmem #(parameter NUMLINES=512, parameter LINESIZE = 256, par assign DataWord = ReadLineTransformed[ReadOffset]; genvar i; generate - for (i=0; i < LINESIZE/WORDSIZE; i++) begin + for (i=0; i < LINESIZE/WORDSIZE; i++) begin:readline assign ReadLineTransformed[i] = ReadLine[(i+1)*WORDSIZE-1:i*WORDSIZE]; end endgenerate @@ -214,7 +214,7 @@ module wtdirectmappedmem #(parameter NUMLINES=512, parameter LINESIZE = 256, par assign DataWord = ReadLineTransformed[ReadOffset]; genvar i; generate - for (i=0; i < LINESIZE/WORDSIZE; i++) begin + for (i=0; i < LINESIZE/WORDSIZE; i++) begin:readline assign ReadLineTransformed[i] = ReadLine[(i+1)*WORDSIZE-1:i*WORDSIZE]; end endgenerate diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index edbaad68..4bd079e9 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -216,7 +216,7 @@ module ahblite ( subwordread swr(.*); // Handle AMO instructions if applicable - generate + generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; amoalu amoalu(.srca(HRDATAW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM), diff --git a/wally-pipelined/src/generic/shift.sv b/wally-pipelined/src/generic/shift.sv index 88152588..70e1076d 100755 --- a/wally-pipelined/src/generic/shift.sv +++ b/wally-pipelined/src/generic/shift.sv @@ -38,13 +38,12 @@ module shift_right #(parameter WIDTH=8) assign stage[0] = A; generate - for (i=0;i<$clog2(WIDTH);i=i+1) - begin : genbit - mux2 #(WIDTH) mux_inst (stage[i], + for (i=0;i<$clog2(WIDTH);i=i+1) begin : genbit + mux2 #(WIDTH) mux_inst (stage[i], {{(WIDTH/(2**(i+1))){1'b0}}, stage[i][WIDTH-1:WIDTH/(2**(i+1))]}, Shift[$clog2(WIDTH)-i-1], stage[i+1]); - end + end endgenerate assign Z = stage[$clog2(WIDTH)]; @@ -60,13 +59,12 @@ module shift_left #(parameter WIDTH=8) assign stage[0] = A; generate - for (i=0;i<$clog2(WIDTH);i=i+1) - begin : genbit - mux2 #(WIDTH) mux_inst (stage[i], + for (i=0;i<$clog2(WIDTH);i=i+1) begin : genbit + mux2 #(WIDTH) mux_inst (stage[i], {stage[i][WIDTH-1-WIDTH/(2**(i+1)):0], {(WIDTH/(2**(i+1))){1'b0}}}, Shift[$clog2(WIDTH)-i-1], stage[i+1]); - end + end endgenerate assign Z = stage[$clog2(WIDTH)]; diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv index 102fbbed..ac2c06dd 100644 --- a/wally-pipelined/src/ieu/alu.sv +++ b/wally-pipelined/src/ieu/alu.sv @@ -42,7 +42,7 @@ module alu #(parameter WIDTH=32) ( assign {carry, presum} = a + condinvb + {{(WIDTH-1){1'b0}},alucontrol[3]}; // support W-type RV64I ADDW/SUBW/ADDIW that sign-extend 32-bit result to 64 bits - generate + generate if (WIDTH==64) assign sum = w64 ? {{32{presum[31]}}, presum[31:0]} : presum; else diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index 44a40045..f041fce6 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -129,7 +129,7 @@ module datapath ( flopenrc #(5) RdWEg(clk, reset, FlushW, ~StallW, RdM, RdW); // handle Store Conditional result if atomic extension supported - generate + generate if (`A_SUPPORTED) assign SCResultW = SquashSCW ? {{(`XLEN-1){1'b0}}, 1'b1} : {{(`XLEN-1){1'b0}}, 1'b0}; else diff --git a/wally-pipelined/src/ifu/SRAM2P1R1W.sv b/wally-pipelined/src/ifu/SRAM2P1R1W.sv index d71f8bc4..046aacc6 100644 --- a/wally-pipelined/src/ifu/SRAM2P1R1W.sv +++ b/wally-pipelined/src/ifu/SRAM2P1R1W.sv @@ -97,11 +97,11 @@ module SRAM2P1R1W // write port generate - for (index = 0; index < Width; index = index + 1) begin + for (index = 0; index < Width; index = index + 1) begin:mem always_ff @ (posedge clk) begin - if (WEN1Q & BitWEN1[index]) begin - memory[WA1Q][index] <= WD1Q[index]; - end + if (WEN1Q & BitWEN1[index]) begin + memory[WA1Q][index] <= WD1Q[index]; + end end end endgenerate diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 4fcefe85..24952edf 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -188,7 +188,7 @@ module ifu ( flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF); // branch and jump predictor - generate + generate if (`BPRED_ENABLED == 1) begin : bpred // I am making the port connection explicit for now as I want to see them and they will be changing. bpred bpred(.*, diff --git a/wally-pipelined/src/ifu/localHistoryPredictor.sv b/wally-pipelined/src/ifu/localHistoryPredictor.sv index 8aaa85c0..6c5c9478 100644 --- a/wally-pipelined/src/ifu/localHistoryPredictor.sv +++ b/wally-pipelined/src/ifu/localHistoryPredictor.sv @@ -67,7 +67,7 @@ module localHistoryPredictor genvar index; generate - for (index = 0; index < 2**m; index = index +1) begin + for (index = 0; index < 2**m; index = index +1) begin:localhist flopenr #(k) LocalHistoryRegister(.clk(clk), .reset(reset), diff --git a/wally-pipelined/src/lsu/dcache.sv b/wally-pipelined/src/lsu/dcache.sv index fec70ef4..e8dfeb5c 100644 --- a/wally-pipelined/src/lsu/dcache.sv +++ b/wally-pipelined/src/lsu/dcache.sv @@ -151,7 +151,7 @@ module dcachecontroller #(parameter LINESIZE = 256) ( genvar i; generate - for (i=0; i < WORDSPERLINE; i++) begin + for (i=0; i < WORDSPERLINE; i++) begin:sb flopenr #(`XLEN) flop(clk, reset, FetchState & (i == FetchWordNum), ReadDataW, DCacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]); end endgenerate diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index 3f57cabb..dc77ec9d 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -138,12 +138,14 @@ module lsuArb assign MemRWMtoLSU = SelPTW ? {HPTWRead, 1'b0} : MemRWM; generate - if (`XLEN == 32) begin + assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw + /* if (`XLEN == 32) begin assign Funct3MtoLSU = SelPTW ? 3'b010 : Funct3M; end else begin assign Funct3MtoLSU = SelPTW ? 3'b011 : Funct3M; - end + end*/ endgenerate + mux2 sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoLSU); assign AtomicMtoLSU = SelPTW ? 2'b00 : AtomicM; assign MemAdrMtoLSU = SelPTW ? HPTWPAdr : MemAdrM; diff --git a/wally-pipelined/src/mmu/pmpadrdec.sv b/wally-pipelined/src/mmu/pmpadrdec.sv index 50d399ae..0a14d832 100644 --- a/wally-pipelined/src/mmu/pmpadrdec.sv +++ b/wally-pipelined/src/mmu/pmpadrdec.sv @@ -76,8 +76,9 @@ module pmpadrdec ( generate assign Mask[1:0] = 2'b11; assign Mask[2] = (AdrMode == NAPOT); // mask has 0s in upper bis for NA4 region - for (i=3; i < `PA_BITS; i=i+1) + for (i=3; i < `PA_BITS; i=i+1) begin:mask assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore + end endgenerate // verilator lint_on UNOPTFLAT diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index ee4b261d..9c7f11da 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -63,12 +63,6 @@ module pmpchecker ( // verilator lint_on UNOPTFLAT logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] genvar i,j; - /* - generate // extract 8-bit chunks from PMPCFG array - for (j=0; j<`PMP_ENTRIES; j = j+8) - assign {PMPCfg[j+7], PMPCfg[j+6], PMPCfg[j+5], PMPCfg[j+4], - PMPCfg[j+3], PMPCfg[j+2], PMPCfg[j+1], PMPCfg[j]} = PMPCFG_ARRAY_REGW[j/8]; - endgenerate */ pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0]( .PhysicalAddress, @@ -80,7 +74,6 @@ module pmpchecker ( .NoLowerMatchOut(NoLowerMatch), .Match, .Active, .L, .X, .W, .R); - // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; diff --git a/wally-pipelined/src/mmu/tlbpriority.sv b/wally-pipelined/src/mmu/tlbpriority.sv index a061f622..5096cae6 100644 --- a/wally-pipelined/src/mmu/tlbpriority.sv +++ b/wally-pipelined/src/mmu/tlbpriority.sv @@ -41,8 +41,9 @@ module tlbpriority #(parameter ENTRIES = 8) ( genvar i; generate assign nolower[0] = 1; - for (i=1; i 0) assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);