Gave names to for loops in generate blocks for ease of reference

wally-pipelined/src/cache/ICacheCntrl.sv

@@ -425,8 +425,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
   // store read data from memory interface before writing into SRAM.
   genvar 				i;
   generate
-    for (i = 0; i < WORDSPERLINE; i++) begin
+    for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer
-      flopenr #(`XLEN) flop(.clk(clk),
+      flopenr #(`XLEN) sb(.clk(clk),
 			    .reset(reset), 
 			    .en(InstrAckF & (i == FetchCount)),
 			    .d(InstrInF),

wally-pipelined/src/cache/dmapped.sv

@@ -106,7 +106,7 @@ module rodirectmappedmem #(parameter NUMLINES=512, parameter LINESIZE = 256, par
     assign DataWord = ReadLineTransformed[ReadOffset];
     genvar i;
     generate
-        for (i=0; i < LINESIZE/WORDSIZE; i++) begin
+        for (i=0; i < LINESIZE/WORDSIZE; i++) begin:readline
             assign ReadLineTransformed[i] = ReadLine[(i+1)*WORDSIZE-1:i*WORDSIZE];
         end
     endgenerate
@@ -214,7 +214,7 @@ module wtdirectmappedmem #(parameter NUMLINES=512, parameter LINESIZE = 256, par
     assign DataWord = ReadLineTransformed[ReadOffset];
     genvar i;
     generate
-        for (i=0; i < LINESIZE/WORDSIZE; i++) begin
+        for (i=0; i < LINESIZE/WORDSIZE; i++) begin:readline
             assign ReadLineTransformed[i] = ReadLine[(i+1)*WORDSIZE-1:i*WORDSIZE];
         end
     endgenerate

wally-pipelined/src/ebu/ahblite.sv

@@ -216,7 +216,7 @@ module ahblite (
   subwordread swr(.*);
 
   // Handle AMO instructions if applicable
-  generate 
+  generate
     if (`A_SUPPORTED) begin
       logic [`XLEN-1:0] AMOResult;
       amoalu amoalu(.srca(HRDATAW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM), 

wally-pipelined/src/generic/shift.sv

@@ -38,13 +38,12 @@ module shift_right #(parameter WIDTH=8)
 
    assign stage[0] = A;   
    generate
-      for (i=0;i<$clog2(WIDTH);i=i+1)
+      for (i=0;i<$clog2(WIDTH);i=i+1) begin : genbit
-	begin : genbit
+	      mux2 #(WIDTH) mux_inst (stage[i], 
-	   mux2 #(WIDTH) mux_inst (stage[i], 
 				   {{(WIDTH/(2**(i+1))){1'b0}}, stage[i][WIDTH-1:WIDTH/(2**(i+1))]}, 
 				   Shift[$clog2(WIDTH)-i-1], 
 				   stage[i+1]);
-	end
+	   end
    endgenerate
    assign Z = stage[$clog2(WIDTH)];   
 
@@ -60,13 +59,12 @@ module shift_left #(parameter WIDTH=8)
    
    assign stage[0] = A;   
    generate
-      for (i=0;i<$clog2(WIDTH);i=i+1)
+      for (i=0;i<$clog2(WIDTH);i=i+1) begin : genbit
-	begin : genbit
+	     mux2 #(WIDTH) mux_inst (stage[i], 
-	   mux2 #(WIDTH) mux_inst (stage[i], 
 				   {stage[i][WIDTH-1-WIDTH/(2**(i+1)):0], {(WIDTH/(2**(i+1))){1'b0}}}, 
 				   Shift[$clog2(WIDTH)-i-1], 
 				   stage[i+1]);
-	end
+	   end
    endgenerate
    assign Z = stage[$clog2(WIDTH)];   
 

wally-pipelined/src/ieu/alu.sv

@@ -42,7 +42,7 @@ module alu #(parameter WIDTH=32) (
   assign {carry, presum} = a + condinvb + {{(WIDTH-1){1'b0}},alucontrol[3]};
   
   // support W-type RV64I ADDW/SUBW/ADDIW that sign-extend 32-bit result to 64 bits
-  generate 
+  generate
     if (WIDTH==64)
       assign sum = w64 ? {{32{presum[31]}}, presum[31:0]} : presum;
     else

wally-pipelined/src/ieu/datapath.sv

@@ -129,7 +129,7 @@ module datapath (
   flopenrc #(5)    RdWEg(clk, reset, FlushW, ~StallW, RdM, RdW);
 
   // handle Store Conditional result if atomic extension supported
-  generate 
+  generate
     if (`A_SUPPORTED)
       assign SCResultW = SquashSCW ? {{(`XLEN-1){1'b0}}, 1'b1} : {{(`XLEN-1){1'b0}}, 1'b0};
     else 

wally-pipelined/src/ifu/SRAM2P1R1W.sv

@@ -97,11 +97,11 @@ module SRAM2P1R1W
   
   // write port
   generate
-    for (index = 0; index < Width; index = index + 1) begin    
+    for (index = 0; index < Width; index = index + 1) begin:mem
       always_ff @ (posedge clk) begin
-	if (WEN1Q & BitWEN1[index]) begin
+	      if (WEN1Q & BitWEN1[index]) begin
-	  memory[WA1Q][index] <= WD1Q[index];
+	        memory[WA1Q][index] <= WD1Q[index];
-	end
+	      end
       end
     end
   endgenerate

wally-pipelined/src/ifu/ifu.sv

@@ -188,7 +188,7 @@ module ifu (
   flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF);
 
   // branch and jump predictor
-  generate 
+  generate
     if (`BPRED_ENABLED == 1) begin : bpred
       // I am making the port connection explicit for now as I want to see them and they will be changing.
       bpred bpred(.*,

wally-pipelined/src/ifu/localHistoryPredictor.sv

@@ -67,7 +67,7 @@ module localHistoryPredictor
 
   genvar 		   index;
   generate
-    for (index = 0; index < 2**m; index = index +1) begin
+    for (index = 0; index < 2**m; index = index +1) begin:localhist
       
       flopenr #(k) LocalHistoryRegister(.clk(clk),
 					.reset(reset),

wally-pipelined/src/lsu/dcache.sv

@@ -151,7 +151,7 @@ module dcachecontroller #(parameter LINESIZE = 256) (
 
     genvar i;
     generate
-        for (i=0; i < WORDSPERLINE; i++) begin
+        for (i=0; i < WORDSPERLINE; i++) begin:sb
             flopenr #(`XLEN) flop(clk, reset, FetchState & (i == FetchWordNum), ReadDataW, DCacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]);
         end
     endgenerate

wally-pipelined/src/lsu/lsuArb.sv

@@ -138,12 +138,14 @@ module lsuArb
   assign MemRWMtoLSU = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
   
   generate
-    if (`XLEN == 32) begin
+    assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
+  /*  if (`XLEN == 32) begin
       assign Funct3MtoLSU = SelPTW ? 3'b010 : Funct3M;
     end else begin
       assign Funct3MtoLSU = SelPTW ? 3'b011 : Funct3M;
-    end
+    end*/
   endgenerate
+  mux2 sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoLSU);
 
   assign AtomicMtoLSU = SelPTW ? 2'b00 : AtomicM;
   assign MemAdrMtoLSU = SelPTW ? HPTWPAdr : MemAdrM;

wally-pipelined/src/mmu/pmpadrdec.sv

@@ -76,8 +76,9 @@ module pmpadrdec (
   generate
     assign Mask[1:0] = 2'b11;
     assign Mask[2] = (AdrMode == NAPOT); // mask has 0s in upper bis for NA4 region
-    for (i=3; i < `PA_BITS; i=i+1) 
+    for (i=3; i < `PA_BITS; i=i+1) begin:mask
       assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore
+    end
    endgenerate
   // verilator lint_on UNOPTFLAT
 

wally-pipelined/src/mmu/pmpchecker.sv

@@ -63,12 +63,6 @@ module pmpchecker (
   // verilator lint_on UNOPTFLAT
   logic [`PMP_ENTRIES-1:0]   PAgePMPAdr;  // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
   genvar i,j;
- /*
-  generate // extract 8-bit chunks from PMPCFG array
-    for (j=0; j<`PMP_ENTRIES; j = j+8)
-      assign {PMPCfg[j+7], PMPCfg[j+6], PMPCfg[j+5], PMPCfg[j+4],
-              PMPCfg[j+3], PMPCfg[j+2], PMPCfg[j+1], PMPCfg[j]} = PMPCFG_ARRAY_REGW[j/8];
-  endgenerate */
 
   pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
     .PhysicalAddress, 
@@ -80,7 +74,6 @@ module pmpchecker (
     .NoLowerMatchOut(NoLowerMatch),
     .Match, .Active, .L, .X, .W, .R);
 
-
   // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
   assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; 
 

wally-pipelined/src/mmu/tlbpriority.sv

@@ -41,8 +41,9 @@ module tlbpriority #(parameter ENTRIES = 8) (
   genvar i;
   generate
     assign nolower[0] = 1;
-    for (i=1; i<ENTRIES; i++) 
+    for (i=1; i<ENTRIES; i++) begin:therm
       assign nolower[i] = nolower[i-1] & ~a[i-1];
+    end
   endgenerate
   // verilator lint_on UNOPTFLAT
   assign y = a & nolower;

wally-pipelined/src/muldiv/div.sv

@@ -299,10 +299,9 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c,
    logic [WIDTH:0] 					  carry_temp;   
    genvar 						  i;
    generate
-      for (i=0;i<WIDTH;i=i+1)
+      for (i=0;i<WIDTH;i=i+1) begin : genbit
-	begin : genbit
+	    fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
-	   fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
+	  end
-	end
    endgenerate
    assign carry = {carry_temp[WIDTH-1:1], 1'b0};     
 

wally-pipelined/src/privileged/csrc.sv

@@ -87,7 +87,7 @@ module csrc #(parameter
     output logic             IllegalCSRCAccessM
   );
 
-  generate 
+  generate
     if (`ZCOUNTERS_SUPPORTED) begin
       //  logic [63:0] TIME_REGW, TIMECMP_REGW;
       logic [63:0] CYCLE_REGW, INSTRET_REGW;

wally-pipelined/src/privileged/csri.sv

@@ -70,7 +70,7 @@ module csri #(parameter
   // MEIP, MTIP, MSIP are read-only
   // SEIP, STIP, SSIP is writable in MIP if S mode exists
   // SSIP is writable in SIP if S mode exists
-  generate 
+  generate
     if (`S_SUPPORTED) begin
       assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writable in MIP (20210108-draft 3.1.9)
       assign SIP_WRITE_MASK = 12'h002; // SSIP is writable in SIP (privileged 20210108-draft 4.1.3)

wally-pipelined/src/privileged/csrn.sv

@@ -49,7 +49,7 @@ module csrn #(parameter
   );
 
   // User mode CSRs below only needed when user mode traps are supported
-  generate  
+  generate
     if (`N_SUPPORTED) begin
       logic WriteUTVECM;
       logic WriteUSCRATCHM, WriteUEPCM;

wally-pipelined/src/privileged/csrs.sv

@@ -66,7 +66,7 @@ module csrs #(parameter
   //logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8
 
   // Supervisor mode CSRs sometimes supported
-  generate  
+  generate
     if (`S_SUPPORTED) begin
       logic WriteSTVECM;
       logic WriteSSCRATCHM, WriteSEPCM;

wally-pipelined/src/privileged/csru.sv

@@ -43,7 +43,7 @@ module csru #(parameter
   );
 
   // Floating Point CSRs in User Mode only needed if Floating Point is supported
-  generate  
+  generate
     if (`F_SUPPORTED | `D_SUPPORTED) begin
       logic [4:0] FFLAGS_REGW;
       logic WriteFFLAGSM, WriteFRMM; //, WriteFCSRM;

wally-pipelined/src/uncore/gpio.sv

@@ -151,7 +151,7 @@ module gpio (
   end
 
   // chip i/o
-  generate 
+  generate
     if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing
       assign input0d = GPIOPinsOut & input_en & output_en;
     else

wally-pipelined/src/uncore/uartPC16550D.sv

@@ -291,7 +291,7 @@ module uartPC16550D(
   // although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop
   generate
     genvar i;
-    for (i=0; i<16; i++) begin
+    for (i=0; i<16; i++) begin:rx
       assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
       if (i > 0)
         assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);