Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Running 16-bit square root cases first in testfloat

Browse Source
This commit is contained in:
David Harris 2022-09-07 11:11:35 -07:00
parent e01b03e9b2
commit b0cf73d19c
3 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/regression/sim-testfloat
View File

@ -9,4 +9,4 @@
# sqrt - test square root
# all - test everything
vsim -do "do testfloat.do rv64fp $1"
vsim -do "do testfloat.do rv64fpquad $1"

2
pipelined/regression/testfloat.do
View File

@ -34,7 +34,7 @@ vlib work
# $num = the added words after the call
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
vsim -voptargs=+acc work.testbenchfp -G TEST=$2 -suppress 4014
vsim -voptargs=+acc work.testbenchfp -G TEST=$2
view wave
#-- display input and output signals as hexidecimal values

10
pipelined/testbench/testbench-fp.sv
View File

@ -585,13 +585,21 @@ module testbenchfp;
end
if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
// reverse order
Tests = {f16sqrt, Tests};
OpCtrl = {`SQRT_OPCTRL, OpCtrl};
WriteInt = {1'b0, WriteInt};
for(int i = 0; i<5; i++) begin
Unit = {`DIVUNIT, Unit};
Fmt = {2'b10, Fmt};
end
/* Tests = {Tests, f16sqrt};
OpCtrl = {OpCtrl, `SQRT_OPCTRL};
WriteInt = {WriteInt, 1'b0};
for(int i = 0; i<5; i++) begin
Unit = {Unit, `DIVUNIT};
Fmt = {Fmt, 2'b10};
end
end */
end
if (TEST === "fma" | TEST === "all") begin // if fma is being tested
Tests = {Tests, f16fma};