From b0cf73d19c4df1245982d0f35a7c6ba23ba6aded Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 7 Sep 2022 11:11:35 -0700
Subject: [PATCH] Running 16-bit square root cases first in testfloat

---
 pipelined/regression/sim-testfloat  |  2 +-
 pipelined/regression/testfloat.do   |  2 +-
 pipelined/testbench/testbench-fp.sv | 10 +++++++++-
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/pipelined/regression/sim-testfloat b/pipelined/regression/sim-testfloat
index 25fe09a1..7f22690c 100755
--- a/pipelined/regression/sim-testfloat
+++ b/pipelined/regression/sim-testfloat
@@ -9,4 +9,4 @@
 # sqrt   - test square root
 # all    - test everything
 
-vsim -do "do testfloat.do rv64fp $1"
+vsim -do "do testfloat.do rv64fpquad $1"
diff --git a/pipelined/regression/testfloat.do b/pipelined/regression/testfloat.do
index 455f8266..00020f77 100644
--- a/pipelined/regression/testfloat.do
+++ b/pipelined/regression/testfloat.do
@@ -34,7 +34,7 @@ vlib work
 # $num = the added words after the call
 vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
 
-vsim -voptargs=+acc work.testbenchfp -G TEST=$2 -suppress 4014
+vsim -voptargs=+acc work.testbenchfp -G TEST=$2
 
 view wave
 #-- display input and output signals as hexidecimal values
diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv
index 4e0755e4..59331179 100644
--- a/pipelined/testbench/testbench-fp.sv
+++ b/pipelined/testbench/testbench-fp.sv
@@ -585,13 +585,21 @@ module testbenchfp;
       end
       if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
         // add the correct tests/op-ctrls/unit/fmt to their lists
+        // reverse order
         Tests = {f16sqrt, Tests};
+        OpCtrl = {`SQRT_OPCTRL, OpCtrl};
+        WriteInt = {1'b0, WriteInt};
+        for(int i = 0; i<5; i++) begin
+          Unit = {`DIVUNIT, Unit};
+          Fmt = {2'b10, Fmt};
+        end
+/*        Tests = {Tests, f16sqrt};
         OpCtrl = {OpCtrl, `SQRT_OPCTRL};
         WriteInt = {WriteInt, 1'b0};
         for(int i = 0; i<5; i++) begin
           Unit = {Unit, `DIVUNIT};
           Fmt = {Fmt, 2'b10};
-        end
+        end */
       end
       if (TEST === "fma"   | TEST === "all") begin // if fma is being tested
         Tests = {Tests, f16fma};