parameterized the caches with the goal of using common rtl for both i and d caches.

pipelined/src/cache/dcache.sv

@@ -25,7 +25,9 @@
 
 `include "wally-config.vh"
 
-module dcache
+module dcache #(parameter integer LINELEN, 
+				parameter integer NUMLINES, 
+				parameter integer NUMWAYS)
   (input logic clk,
    input logic 				   reset,
    input logic 				   CPUBusy,
@@ -52,8 +54,8 @@ module dcache
    output logic [`PA_BITS-1:0] DCacheBusAdr,
 
 
-   input logic [`DCACHE_LINELENINBITS-1:0] DCacheMemWriteData,
-   output logic [`XLEN-1:0] 				ReadDataLineSetsM [(`DCACHE_LINELENINBITS/`XLEN)-1:0],
+   input logic [LINELEN-1:0]   DCacheMemWriteData,
+   output logic [`XLEN-1:0]    ReadDataLineSetsM [(LINELEN/`XLEN)-1:0],
 
    output logic 			   DCacheStall,
 
@@ -62,9 +64,6 @@ module dcache
    output logic 			   DCacheAccess
    );
 
-  localparam integer 						LINELEN = `DCACHE_LINELENINBITS;
-  localparam integer 						NUMLINES = `DCACHE_WAYSIZEINBYTES*8/LINELEN;
-  localparam integer 						NUMWAYS = `DCACHE_NUMWAYS;
 
   localparam integer 						LINEBYTELEN = LINELEN/8;
   localparam integer 						OFFSETLEN = $clog2(LINEBYTELEN);

pipelined/src/cache/icache.sv

@@ -25,14 +25,15 @@
 
 `include "wally-config.vh"
 
-module icache
+module icache #(parameter integer LINELEN, 
+				parameter integer NUMLINES,
+				parameter integer NUMWAYS)
   (
    // Basic pipeline stuff
    input logic 				  clk, reset,
    input logic 				  CPUBusy,
 
    // mmu
-   //input logic 								CacheableF,
    input logic [1:0] 		  IfuRWF,
 
    // cpu side 
@@ -43,7 +44,7 @@ module icache
 
    // bus fsm interface
    input logic 				  IgnoreRequest,
-   input logic [`ICACHE_LINELENINBITS-1:0] ICacheMemWriteData,
+   input logic [LINELEN-1:0]  ICacheMemWriteData,
    output logic 			  ICacheFetchLine,
 
    (* mark_debug = "true" *) input logic ICacheBusAck,
@@ -57,8 +58,6 @@ module icache
    );
 
   // Configuration parameters
-  localparam integer 		  LINELEN = `ICACHE_LINELENINBITS;
-  localparam integer 		  NUMLINES = `ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS;
   localparam integer 		  LINEBYTELEN = LINELEN/8;
 
   localparam integer 		  OFFSETLEN = $clog2(LINEBYTELEN);
@@ -69,7 +68,7 @@ module icache
   localparam WORDSPERLINE = LINELEN/`XLEN;
   localparam LOGWPL = $clog2(WORDSPERLINE);
 
-  localparam integer 		  NUMWAYS = `ICACHE_NUMWAYS;
+
   
 
   // Input signals to cache memory
@@ -86,7 +85,7 @@ module icache
   
   logic [LINELEN-1:0] 		  ReadDataLineWayMasked [NUMWAYS-1:0];
 
-  logic [31:0] 				  ReadLineSetsF [`ICACHE_LINELENINBITS/16-1:0];
+  logic [31:0] 				  ReadLineSetsF [LINELEN/16-1:0];
   
   logic [NUMWAYS-1:0] 		  SRAMWayWriteEnable;
 

pipelined/src/ifu/ifu.sv

@@ -243,7 +243,10 @@ module ifu (
 	  logic [1:0] IfuRWF;
 	  assign IfuRWF = CacheableF ? 2'b10 : 2'b00;
 	  
-	  icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
+	  icache #(.LINELEN(`ICACHE_LINELENINBITS),
+			   .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
+			   .NUMWAYS(`ICACHE_NUMWAYS))
+	  icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
 					.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
 					.ICacheFetchLine,
 					.IfuRWF(IfuRWF), //aways read

pipelined/src/lsu/lsu.sv

@@ -306,7 +306,9 @@ module lsu
 
   generate
     if(`MEM_DCACHE) begin : dcache
-      dcache dcache(.clk, .reset, .CPUBusy,
+      dcache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
+			   .NUMWAYS(`DCACHE_NUMWAYS)) 
+	  dcache(.clk, .reset, .CPUBusy,
             .LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM, .PreLsuPAdrM(PreLsuPAdrM[11:0]), // still don't like this name PreLsuPAdrM, not always physical
             .FinalWriteDataM, .ReadDataWordM, .DCacheStall,
             .DCacheMiss, .DCacheAccess,