diff --git a/pipelined/src/cache/dcache.sv b/pipelined/src/cache/dcache.sv
index d2c47169..361ba8fa 100644
--- a/pipelined/src/cache/dcache.sv
+++ b/pipelined/src/cache/dcache.sv
@@ -25,46 +25,45 @@
 
 `include "wally-config.vh"
 
-module dcache
+module dcache #(parameter integer LINELEN, 
+				parameter integer NUMLINES, 
+				parameter integer NUMWAYS)
   (input logic clk,
-   input logic 								reset,
-   input logic 								CPUBusy,
+   input logic 				   reset,
+   input logic 				   CPUBusy,
 
    // mmu
-   input logic 								CacheableM,
+   input logic 				   CacheableM,
    // cpu side
-   input logic [1:0] 						LsuRWM,
-   input logic [1:0] 						LsuAtomicM,
-   input logic 								FlushDCacheM,
-   input logic [11:0] 						LsuAdrE, // virtual address, but we only use the lower 12 bits.
-   input logic [`PA_BITS-1:0] 				LsuPAdrM, // physical address
-   input logic [11:0] 						PreLsuPAdrM, // physical or virtual address   
-   input logic [`XLEN-1:0] 					FinalWriteDataM,
-   output logic [`XLEN-1:0] 				ReadDataWordM,
-   output logic 							DCacheCommittedM, 
+   input logic [1:0] 		   LsuRWM,
+   input logic [1:0] 		   LsuAtomicM,
+   input logic 				   FlushDCacheM,
+   input logic [11:0] 		   LsuAdrE, // virtual address, but we only use the lower 12 bits.
+   input logic [`PA_BITS-1:0]  LsuPAdrM, // physical address
+   input logic [11:0] 		   PreLsuPAdrM, // physical or virtual address   
+   input logic [`XLEN-1:0] 	   FinalWriteDataM,
+   output logic [`XLEN-1:0]    ReadDataWordM,
+   output logic 			   DCacheCommittedM, 
 
    // Bus fsm interface
-   input logic 								IgnoreRequest,
-   output logic 							DCacheFetchLine,
-   output logic 							DCacheWriteLine,
+   input logic 				   IgnoreRequest,
+   output logic 			   DCacheFetchLine,
+   output logic 			   DCacheWriteLine,
 
-   input logic 								DCacheBusAck,
-   output logic [`PA_BITS-1:0] 				DCacheBusAdr,
+   input logic 				   DCacheBusAck,
+   output logic [`PA_BITS-1:0] DCacheBusAdr,
 
 
-   input logic [`DCACHE_LINELENINBITS-1:0] DCacheMemWriteData,
-   output logic [`XLEN-1:0] 				ReadDataLineSetsM [(`DCACHE_LINELENINBITS/`XLEN)-1:0],
+   input logic [LINELEN-1:0]   DCacheMemWriteData,
+   output logic [`XLEN-1:0]    ReadDataLineSetsM [(LINELEN/`XLEN)-1:0],
 
-   output logic 							DCacheStall,
+   output logic 			   DCacheStall,
 
    // to performance counters
-   output logic 							DCacheMiss,
-   output logic 							DCacheAccess
+   output logic 			   DCacheMiss,
+   output logic 			   DCacheAccess
    );
 
-  localparam integer 						LINELEN = `DCACHE_LINELENINBITS;
-  localparam integer 						NUMLINES = `DCACHE_WAYSIZEINBYTES*8/LINELEN;
-  localparam integer 						NUMWAYS = `DCACHE_NUMWAYS;
 
   localparam integer 						LINEBYTELEN = LINELEN/8;
   localparam integer 						OFFSETLEN = $clog2(LINEBYTELEN);
diff --git a/pipelined/src/cache/icache.sv b/pipelined/src/cache/icache.sv
index f6ad7484..4af94fe1 100644
--- a/pipelined/src/cache/icache.sv
+++ b/pipelined/src/cache/icache.sv
@@ -25,31 +25,32 @@
 
 `include "wally-config.vh"
 
-module icache
+module icache #(parameter integer LINELEN, 
+				parameter integer NUMLINES,
+				parameter integer NUMWAYS)
   (
    // Basic pipeline stuff
-   input logic 								clk, reset,
-   input logic 								CPUBusy,
+   input logic 				  clk, reset,
+   input logic 				  CPUBusy,
 
    // mmu
-   //input logic 								CacheableF,
-   input logic [1:0] 						IfuRWF,
+   input logic [1:0] 		  IfuRWF,
 
    // cpu side 
-   input logic 								InvalidateICacheM,
-   input logic [11:0] 						PCNextF,
-   input logic [`PA_BITS-1:0] 				PCPF,
-   input logic [`XLEN-1:0] 					PCF,
+   input logic 				  InvalidateICacheM,
+   input logic [11:0] 		  PCNextF,
+   input logic [`PA_BITS-1:0] PCPF,
+   input logic [`XLEN-1:0] 	  PCF,
 
    // bus fsm interface
-   input logic 								IgnoreRequest,
-   input logic [`ICACHE_LINELENINBITS-1:0] ICacheMemWriteData,
-   output logic 							ICacheFetchLine,
+   input logic 				  IgnoreRequest,
+   input logic [LINELEN-1:0]  ICacheMemWriteData,
+   output logic 			  ICacheFetchLine,
 
-   (* mark_debug = "true" *) input logic 	ICacheBusAck,
+   (* mark_debug = "true" *) input logic ICacheBusAck,
    (* mark_debug = "true" *) output logic [`PA_BITS-1:0] ICacheBusAdr,
    // High if the icache is requesting a stall
-   output logic 							ICacheStallF,
+   output logic 			  ICacheStallF,
   
    // The raw (not decompressed) instruction that was requested
    // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
@@ -57,8 +58,6 @@ module icache
    );
 
   // Configuration parameters
-  localparam integer 		  LINELEN = `ICACHE_LINELENINBITS;
-  localparam integer 		  NUMLINES = `ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS;
   localparam integer 		  LINEBYTELEN = LINELEN/8;
 
   localparam integer 		  OFFSETLEN = $clog2(LINEBYTELEN);
@@ -69,7 +68,7 @@ module icache
   localparam WORDSPERLINE = LINELEN/`XLEN;
   localparam LOGWPL = $clog2(WORDSPERLINE);
 
-  localparam integer 		  NUMWAYS = `ICACHE_NUMWAYS;
+
   
 
   // Input signals to cache memory
@@ -86,7 +85,7 @@ module icache
   
   logic [LINELEN-1:0] 		  ReadDataLineWayMasked [NUMWAYS-1:0];
 
-  logic [31:0] 				  ReadLineSetsF [`ICACHE_LINELENINBITS/16-1:0];
+  logic [31:0] 				  ReadLineSetsF [LINELEN/16-1:0];
   
   logic [NUMWAYS-1:0] 		  SRAMWayWriteEnable;
 
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 8d963176..9d1b7a7e 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -243,7 +243,10 @@ module ifu (
 	  logic [1:0] IfuRWF;
 	  assign IfuRWF = CacheableF ? 2'b10 : 2'b00;
 	  
-	  icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
+	  icache #(.LINELEN(`ICACHE_LINELENINBITS),
+			   .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
+			   .NUMWAYS(`ICACHE_NUMWAYS))
+	  icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
 					.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
 					.ICacheFetchLine,
 					.IfuRWF(IfuRWF), //aways read
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 876c2d89..ebb4cc05 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -306,7 +306,9 @@ module lsu
 
   generate
     if(`MEM_DCACHE) begin : dcache
-      dcache dcache(.clk, .reset, .CPUBusy,
+      dcache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
+			   .NUMWAYS(`DCACHE_NUMWAYS)) 
+	  dcache(.clk, .reset, .CPUBusy,
             .LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM, .PreLsuPAdrM(PreLsuPAdrM[11:0]), // still don't like this name PreLsuPAdrM, not always physical
             .FinalWriteDataM, .ReadDataWordM, .DCacheStall,
             .DCacheMiss, .DCacheAccess,