From afc693424990a4a672768e3979d9f2a8d8433af5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 27 Sep 2022 11:34:33 -0500 Subject: [PATCH] Possible fix to the bus cache interaction. --- pipelined/src/cache/cachefsm.sv | 12 ++++++------ pipelined/src/ebu/buscachefsm.sv | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 2f748d2f..58ae7afb 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -193,14 +193,14 @@ module cachefsm assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls -// assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck); - assign CacheBusRW[1] = CurrState == STATE_READY & DoAnyMiss; -// assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | -// (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | -// (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) | -// (CurrState == STATE_FLUSH_CHECK & VictimDirty); + assign CacheBusRW[1] = (CurrState == STATE_READY & DoAnyMiss) | (CurrState == STATE_MISS_FETCH_WDV & ~CacheBusAck); +// assign CacheBusRW[1] = CurrState == STATE_READY & DoAnyMiss; assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | + (CurrState == STATE_MISS_EVICT_DIRTY & ~CacheBusAck) | + (CurrState == STATE_FLUSH_WRITE_BACK & ~CacheBusAck) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); +// assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | +// (CurrState == STATE_FLUSH_CHECK & VictimDirty); // **** can this be simplified? assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. // use the raw requests as we don't want DCacheTrapM in the critical path diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 106ec678..6d4e3e03 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -140,8 +140,8 @@ module buscachefsm #(parameter integer WordCountThreshold, // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW)) | - (CurrState == DATA_PHASE & ~HREADY) | - (CacheAccess & ~|WordCount & |CacheBusRW) ? AHB_NONSEQ : // if we have a pipelined request + (CurrState == DATA_PHASE & ~HREADY) | // *** this is wrong. + (CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_EVICT & |WordCount);