From af619dcd75b02b2e985593b6da12ab725baae264 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 6 Jul 2021 18:56:25 -0400
Subject: [PATCH] Added ASID matching for CAM

---
 wally-pipelined/src/mmu/tlbcamline.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/mmu/tlbcamline.sv b/wally-pipelined/src/mmu/tlbcamline.sv
index 95bc57fe..d845365d 100644
--- a/wally-pipelined/src/mmu/tlbcamline.sv
+++ b/wally-pipelined/src/mmu/tlbcamline.sv
@@ -72,7 +72,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
       assign Match0 = (Query0 == Key0) || (PageType[0]); // least signifcant section
       assign Match1 = (Query1 == Key1);
 
-      assign Match = Match0 & Match1 & Valid;
+      assign Match = Match0 & Match1 & MatchASID & Valid;
     end else begin
 
       logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3;
@@ -89,7 +89,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
       assign Match2 = (Query2 == Key2) || (PageType > 2'd2);
       assign Match3 = (Query3 == Key3) || SV39Mode; // this should always match in sv39 because they aren't used
       
-      assign Match = Match0 & Match1 & Match2 & Match3 & Valid;
+      assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid;
     end
   endgenerate