From af435ab59192e6f3cd5a7a013e6d5fe3edb0b6c6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 23 Mar 2022 10:26:17 -0500 Subject: [PATCH] Another change required for forcing to work correctly with MIE/MIP and SIE/SIP. --- pipelined/src/privileged/csri.sv | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 8a3f42fd..b3f0f157 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -95,20 +95,22 @@ module csri #(parameter // else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field // restricted views of registers - // Add MEIP read-only signal - assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; + assign IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; + + always_comb begin:regs + // Add MEIP read-only signal // Machine Mode - assign MIP_REGW = IP_REGW; - assign MIE_REGW = IE_REGW; + MIP_REGW = IP_REGW; + MIE_REGW = IE_REGW; - // Supervisor mode - if (`S_SUPPORTED) begin - assign SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible - assign SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; - end else begin - assign SIP_REGW = 12'b0; - assign SIE_REGW = 12'b0; + // Supervisor mode + if (`S_SUPPORTED) begin + SIP_REGW = IP_REGW & MIDELEG_REGW[11:0] & 'h222; // only delegated interrupts visible + SIE_REGW = IE_REGW & MIDELEG_REGW[11:0] & 'h222; + end else begin + SIP_REGW = 12'b0; + SIE_REGW = 12'b0; + end end - endmodule