Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/src/fpu/fpu.sv

@@ -237,7 +237,7 @@ module fpu (
    logic fpdivClk;
    
    clockgater fpdivclkg(.E(FDivStartE),
-			.SE(DivBusyM),
+			.SE(1'b0),
 			.CLK(clk),
 			.ECLK(fpdivClk));
    

wally-pipelined/src/generic/clockgater.sv

@@ -38,8 +38,10 @@ module clockgater
   logic 	enable_q;
   
 
-  always @(~CLK) begin
-    enable_q <= E | SE;
+  always_latch begin
+    if(~CLK) begin
+      enable_q <= E | SE;
+    end
   end
   assign ECLK = enable_q & CLK;
 

wally-pipelined/src/ifu/globalHistoryPredictor.sv

@@ -53,6 +53,8 @@ module globalHistoryPredictor
   logic 		   BPClassWrongNonCFI;
   logic 		   BPClassWrongCFI;
   logic 		   BPClassRightNonCFI;
+  logic 		   BPClassRightBPWrong;
+  logic 		   BPClassRightBPRight;
 
   logic [6:0] 		   GHRMuxSel;
   logic 		   GHRUpdateEN;

wally-pipelined/src/ifu/gsharePredictor.sv

@@ -53,6 +53,8 @@ module gsharePredictor
   logic 		   BPClassWrongNonCFI;
   logic 		   BPClassWrongCFI;
   logic 		   BPClassRightNonCFI;
+  logic 		   BPClassRightBPWrong;
+  logic 		   BPClassRightBPRight;
 
   logic [6:0] 		   GHRMuxSel;
   logic 		   GHRUpdateEN;