From e50a1ef5e4582e8fa0e96f6d54c9821379f124dc Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Wed, 2 Jun 2021 09:33:24 -0500
Subject: [PATCH] Fixed a few lint errors, clock gater was wrong, missing
 signal definitions in branch predictor.

---
 wally-pipelined/src/fpu/fpu.sv                    | 2 +-
 wally-pipelined/src/generic/clockgater.sv         | 6 ++++--
 wally-pipelined/src/ifu/globalHistoryPredictor.sv | 2 ++
 wally-pipelined/src/ifu/gsharePredictor.sv        | 2 ++
 4 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv
index e303f205..0a2de521 100755
--- a/wally-pipelined/src/fpu/fpu.sv
+++ b/wally-pipelined/src/fpu/fpu.sv
@@ -237,7 +237,7 @@ module fpu (
    logic fpdivClk;
    
    clockgater fpdivclkg(.E(FDivStartE),
-			.SE(DivBusyM),
+			.SE(1'b0),
 			.CLK(clk),
 			.ECLK(fpdivClk));
    
diff --git a/wally-pipelined/src/generic/clockgater.sv b/wally-pipelined/src/generic/clockgater.sv
index c06a1cbd..f54e1e3d 100644
--- a/wally-pipelined/src/generic/clockgater.sv
+++ b/wally-pipelined/src/generic/clockgater.sv
@@ -38,8 +38,10 @@ module clockgater
   logic 	enable_q;
   
 
-  always @(~CLK) begin
-    enable_q <= E | SE;
+  always_latch begin
+    if(~CLK) begin
+      enable_q <= E | SE;
+    end
   end
   assign ECLK = enable_q & CLK;
 
diff --git a/wally-pipelined/src/ifu/globalHistoryPredictor.sv b/wally-pipelined/src/ifu/globalHistoryPredictor.sv
index 516de633..16964bd8 100644
--- a/wally-pipelined/src/ifu/globalHistoryPredictor.sv
+++ b/wally-pipelined/src/ifu/globalHistoryPredictor.sv
@@ -53,6 +53,8 @@ module globalHistoryPredictor
   logic 		   BPClassWrongNonCFI;
   logic 		   BPClassWrongCFI;
   logic 		   BPClassRightNonCFI;
+  logic 		   BPClassRightBPWrong;
+  logic 		   BPClassRightBPRight;
 
   logic [6:0] 		   GHRMuxSel;
   logic 		   GHRUpdateEN;
diff --git a/wally-pipelined/src/ifu/gsharePredictor.sv b/wally-pipelined/src/ifu/gsharePredictor.sv
index b4a60827..36e54d4b 100644
--- a/wally-pipelined/src/ifu/gsharePredictor.sv
+++ b/wally-pipelined/src/ifu/gsharePredictor.sv
@@ -53,6 +53,8 @@ module gsharePredictor
   logic 		   BPClassWrongNonCFI;
   logic 		   BPClassWrongCFI;
   logic 		   BPClassRightNonCFI;
+  logic 		   BPClassRightBPWrong;
+  logic 		   BPClassRightBPRight;
 
   logic [6:0] 		   GHRMuxSel;
   logic 		   GHRUpdateEN;