From ac94b55e7432e0ebe97fb33811d2a0d574b0f7f2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 21 Dec 2022 09:00:09 -0600
Subject: [PATCH] Fixed minor bug in PLIC. reading interrupt source 0 should
 not return x.  it should provide produce 0. Switched to even simplier PC+2/4
 logic.

---
 pipelined/src/ifu/ifu.sv         | 4 ++--
 pipelined/src/uncore/plic_apb.sv | 5 +++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index f48c0c88..6248d3a3 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -299,11 +299,9 @@ module ifu (
   // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
   // Speeds up critical path as compared to selecting adder input based on CompressedF
   // *** consider gating PCPlusUpperF to provide the reset.
-/* -----\/----- EXCLUDED -----\/-----
   assign PCPlus2or4F[0] = '0;
   assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]);
   assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlusUpperF;
- -----/\----- EXCLUDED -----/\----- */
 /* -----\/----- EXCLUDED -----\/-----
   assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0];
  -----/\----- EXCLUDED -----/\----- */
@@ -311,12 +309,14 @@ module ifu (
   // *** There is actually a bug in the regression test.  We fetched an address which returns data with
   // an X.  This version of the code does not die because if CompressedF is an X it just defaults to the last
   // option.  The above code would work, but propagates the x.
+/* -----\/----- EXCLUDED -----\/-----
   always_comb
     if(reset) PCPlus2or4F = '0;
     else if (CompressedF) // add 2
       if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00}; 
       else        PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
     else          PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
+ -----/\----- EXCLUDED -----/\----- */
 
 
   ////////////////////////////////////////////////////////////////////////////////////////////////
diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv
index 7b3a9585..fd7a4d8f 100644
--- a/pipelined/src/uncore/plic_apb.sv
+++ b/pipelined/src/uncore/plic_apb.sv
@@ -59,7 +59,7 @@ module plic_apb (
   input  logic             UARTIntr,GPIOIntr,
     (* mark_debug = "true" *)  output logic             MExtInt, SExtInt);
 
-  logic memwrite, memread, initTrans;
+  logic memwrite, memread;
   logic [23:0] entry;
   (* mark_debug = "true" *) logic [31:0] Din, Dout;
 
@@ -130,7 +130,8 @@ module plic_apb (
       // Read synchronously because a read can have side effect of changing intInProgress
       if (memread)
         casez(entry)
-          24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};
+          24'h000000: Dout <= #1 32'b0;  // there is no intPriority[0]
+          24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};		  
           `ifdef PLIC_NUM_SRC_LT_32
           24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0};
           24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0};