diff --git a/wally-pipelined/regression/lint-wally b/wally-pipelined/regression/lint-wally
index 631a172b..71edc0d5 100755
--- a/wally-pipelined/regression/lint-wally
+++ b/wally-pipelined/regression/lint-wally
@@ -7,7 +7,7 @@ verilator=`which verilator`
 basepath=$(dirname $0)/..
 for config in rv64g rv32g; do
     echo "$config linting..."
-    if !($verilator --lint-only --Wall "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv --relative-includes); then
+    if !($verilator --lint-only --Wall "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
diff --git a/wally-pipelined/regression/wally-pipelined-batch.do b/wally-pipelined/regression/wally-pipelined-batch.do
index 242b33db..30abbd7b 100644
--- a/wally-pipelined/regression/wally-pipelined-batch.do
+++ b/wally-pipelined/regression/wally-pipelined-batch.do
@@ -32,7 +32,7 @@ vlib work_${1}_${2}
 
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined-batch.do ../config/rv32ic rv32ic
-vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv -suppress 2583
+vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do
index 477e3a12..50177ae2 100644
--- a/wally-pipelined/regression/wally-pipelined.do
+++ b/wally-pipelined/regression/wally-pipelined.do
@@ -37,7 +37,7 @@ vlib work
 #}
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vlog -lint +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv -suppress 2583
+vlog -lint +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
 vopt +acc work.testbench -G TEST=$2 -o workopt 
 vsim workopt
 
diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv
index fa115586..5a952129 100644
--- a/wally-pipelined/src/cache/cachereplacementpolicy.sv
+++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv
@@ -46,7 +46,7 @@ module cachereplacementpolicy
   always_ff @(posedge clk, posedge reset) begin
     if (reset) begin
       for(int index = 0; index < NUMLINES; index++)
-	      ReplacementBits[index] <= '0;
+	      ReplacementBits[index] = '0;
     end else begin
       BlockReplacementBits <= ReplacementBits[RAdr];
       if (LRUWriteEn) begin
diff --git a/wally-pipelined/src/generic/flop.sv b/wally-pipelined/src/generic/flop.sv
deleted file mode 100644
index fc0bf430..00000000
--- a/wally-pipelined/src/generic/flop.sv
+++ /dev/null
@@ -1,123 +0,0 @@
-///////////////////////////////////////////
-// flop.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: arious flavors of flip-flops
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-`include "wally-config.vh"
-/* verilator lint_off DECLFILENAME */
-
-// ordinary flip-flop
-module flop #(parameter WIDTH = 8) ( 
-  input  logic             clk,
-  input  logic [WIDTH-1:0] d, 
-  output logic [WIDTH-1:0] q);
-
-  always_ff @(posedge clk)
-    q <= #1 d;
-endmodule
-
-// flop with asynchronous reset
-module flopr #(parameter WIDTH = 8) ( 
-  input  logic             clk, reset,
-  input  logic [WIDTH-1:0] d, 
-  output logic [WIDTH-1:0] q);
-
-  always_ff @(posedge clk, posedge reset)
-    if (reset) q <= #1 0;
-    else       q <= #1 d;
-endmodule
-
-// flop with enable
-module flopen #(parameter WIDTH = 8) (
-  input  logic             clk, en,
-  input  logic [WIDTH-1:0] d, 
-  output logic [WIDTH-1:0] q);
-
-  always_ff @(posedge clk)
-    if (en) q <= #1 d;
-endmodule
-
-// flop with enable, asynchronous reset, synchronous clear
-module flopenrc #(parameter WIDTH = 8) (
-  input  logic             clk, reset, clear, en,
-  input  logic [WIDTH-1:0] d, 
-  output logic [WIDTH-1:0] q);
-
-  always_ff @(posedge clk, posedge reset)
-    if (reset)   q <= #1 0;
-    else if (en) 
-      if (clear) q <= #1 0;
-      else       q <= #1 d;
-endmodule
-
-// flop with enable, asynchronous reset
-module flopenr #(parameter WIDTH = 8) (
-  input  logic             clk, reset, en,
-  input  logic [WIDTH-1:0] d, 
-  output logic [WIDTH-1:0] q);
-
-  always_ff @(posedge clk, posedge reset)
-    if (reset)   q <= #1 0;
-    else if (en) q <= #1 d;
-endmodule
-
-// flop with enable, asynchronous set
-module flopens #(parameter WIDTH = 8) (
-  input  logic             clk, set, en,
-  input  logic [WIDTH-1:0] d, 
-  output logic [WIDTH-1:0] q);
-
-  always_ff @(posedge clk, posedge set)
-    if (set)   q <= #1 1;
-    else if (en) q <= #1 d;
-endmodule
-
-
-// flop with enable, asynchronous load
-module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
-  input  logic clk, load, en,
-  input  TYPE d,
-  input  TYPE val,
-  output TYPE q);
-
-  always_ff @(posedge clk, posedge load)
-    if (load)    q <= #1 val;
-    else if (en) q <= #1 d;
-endmodule
-
-// flop with asynchronous reset, synchronous clear
-module floprc #(parameter WIDTH = 8) (
-  input  logic clk,
-  input  logic reset,
-  input  logic clear,
-  input  logic [WIDTH-1:0] d, 
-  output logic [WIDTH-1:0] q);
-
-  always_ff @(posedge clk, posedge reset)
-    if (reset) q <= #1 0;
-    else       
-      if (clear) q <= #1 0;
-      else       q <= #1 d;
-endmodule
-
-/* verilator lint_on DECLFILENAME */