forked from Github_Repos/cvw
More renaming.
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@ -68,7 +68,7 @@ module ahbinterface #(parameter WRITEABLE = 0)
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assign HWSTRB = '0;
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assign HWSTRB = '0;
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end
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end
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AHBBusfsm busfsm(.HCLK, .HRESETn, .RW,
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busfsm busfsm(.HCLK, .HRESETn, .RW,
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.BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY,
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.BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY,
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.HTRANS, .HWRITE);
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.HTRANS, .HWRITE);
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endmodule
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endmodule
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@ -82,7 +82,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
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mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
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mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
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AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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.HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
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.HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
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.CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
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.CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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@ -31,7 +31,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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// HCLK and clk must be the same clock!
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// HCLK and clk must be the same clock!
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module AHBBuscachefsm #(parameter integer WordCountThreshold,
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module buscachefsm #(parameter integer WordCountThreshold,
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parameter integer LOGWPL, parameter logic CACHE_ENABLED )
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parameter integer LOGWPL, parameter logic CACHE_ENABLED )
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(input logic HCLK,
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(input logic HCLK,
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input logic HRESETn,
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input logic HRESETn,
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@ -31,7 +31,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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// HCLK and clk must be the same clock!
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// HCLK and clk must be the same clock!
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module AHBBusfsm
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module busfsm
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(input logic HCLK,
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(input logic HCLK,
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input logic HRESETn,
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input logic HRESETn,
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@ -251,7 +251,7 @@ module ifu (
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flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
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flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
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AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn,
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busfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn,
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.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
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.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
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assign IFUHBURST = 3'b0;
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assign IFUHBURST = 3'b0;
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@ -293,7 +293,8 @@ module lsu (
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ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY),
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ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY),
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.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
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.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
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.HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM);
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.HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
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.CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM);
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assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
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assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
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assign LSUHBURST = 3'b0;
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assign LSUHBURST = 3'b0;
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