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More renaming.

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This commit is contained in:
Ross Thompson 2022-08-31 14:49:08 -05:00
parent 6e85f850a4
commit ab4c75cbf5
6 changed files with 7 additions and 6 deletions
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2
pipelined/src/ebu/abhinterface.sv
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@ -68,7 +68,7 @@ module ahbinterface #(parameter WRITEABLE = 0)
assign HWSTRB = '0; assign HWSTRB = '0;
end end
AHBBusfsm busfsm(.HCLK, .HRESETn, .RW, busfsm busfsm(.HCLK, .HRESETn, .RW,
.BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY, .BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY,
.HTRANS, .HWRITE); .HTRANS, .HWRITE);
endmodule endmodule

2
pipelined/src/ebu/ahbcacheinterface.sv
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@ -82,7 +82,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE)); mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
.HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, .HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
.CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed, .CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
.HREADY, .HTRANS, .HWRITE, .HBURST); .HREADY, .HTRANS, .HWRITE, .HBURST);

2
pipelined/src/ebu/AHBBuscachefsm.sv → pipelined/src/ebu/buscachefsm.sv
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@ -31,7 +31,7 @@
`include "wally-config.vh" `include "wally-config.vh"
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module AHBBuscachefsm #(parameter integer WordCountThreshold, module buscachefsm #(parameter integer WordCountThreshold,
parameter integer LOGWPL, parameter logic CACHE_ENABLED ) parameter integer LOGWPL, parameter logic CACHE_ENABLED )
(input logic HCLK, (input logic HCLK,
input logic HRESETn, input logic HRESETn,

2
pipelined/src/ebu/AHBBusfsm.sv → pipelined/src/ebu/busfsm.sv
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@ -31,7 +31,7 @@
`include "wally-config.vh" `include "wally-config.vh"
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module AHBBusfsm module busfsm
(input logic HCLK, (input logic HCLK,
input logic HRESETn, input logic HRESETn,

2
pipelined/src/ifu/ifu.sv
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@ -251,7 +251,7 @@ module ifu (
flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0])); flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn, busfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn,
.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE)); .BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
assign IFUHBURST = 3'b0; assign IFUHBURST = 3'b0;

3
pipelined/src/lsu/lsu.sv
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@ -293,7 +293,8 @@ module lsu (
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY), ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY),
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
.HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM); .HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
.CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM);
assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
assign LSUHBURST = 3'b0; assign LSUHBURST = 3'b0;