diff --git a/pipelined/src/ebu/abhinterface.sv b/pipelined/src/ebu/abhinterface.sv
index d2d23703..d2973533 100644
--- a/pipelined/src/ebu/abhinterface.sv
+++ b/pipelined/src/ebu/abhinterface.sv
@@ -68,7 +68,7 @@ module ahbinterface #(parameter WRITEABLE = 0)
     assign HWSTRB = '0;
   end    
 
-  AHBBusfsm busfsm(.HCLK, .HRESETn, .RW,
+  busfsm busfsm(.HCLK, .HRESETn, .RW,
     .BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY,
     .HTRANS, .HWRITE);
 endmodule
diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv
index 758e2969..cfd78506 100644
--- a/pipelined/src/ebu/ahbcacheinterface.sv
+++ b/pipelined/src/ebu/ahbcacheinterface.sv
@@ -82,7 +82,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
 
   mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
 
-  AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
+  buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
     .HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
     .CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
 	.HREADY, .HTRANS, .HWRITE, .HBURST);
diff --git a/pipelined/src/ebu/AHBBuscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv
similarity index 99%
rename from pipelined/src/ebu/AHBBuscachefsm.sv
rename to pipelined/src/ebu/buscachefsm.sv
index d8f78653..8435b3ef 100644
--- a/pipelined/src/ebu/AHBBuscachefsm.sv
+++ b/pipelined/src/ebu/buscachefsm.sv
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 // HCLK and clk must be the same clock!
-module AHBBuscachefsm #(parameter integer   WordCountThreshold,
+module buscachefsm #(parameter integer   WordCountThreshold,
    parameter integer LOGWPL, parameter logic CACHE_ENABLED )
   (input logic               HCLK,
    input logic               HRESETn,
diff --git a/pipelined/src/ebu/AHBBusfsm.sv b/pipelined/src/ebu/busfsm.sv
similarity index 99%
rename from pipelined/src/ebu/AHBBusfsm.sv
rename to pipelined/src/ebu/busfsm.sv
index b88d5ed4..894630a6 100644
--- a/pipelined/src/ebu/AHBBusfsm.sv
+++ b/pipelined/src/ebu/busfsm.sv
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 // HCLK and clk must be the same clock!
-module AHBBusfsm 
+module busfsm 
   (input logic        HCLK,
    input logic        HRESETn,
 
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index facf465d..a6bb6a05 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -251,7 +251,7 @@ module ifu (
       flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
 
 
-      AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn,
+      busfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn,
                        .BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
           
       assign IFUHBURST = 3'b0;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 0e0b17d2..7f1f491a 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -293,7 +293,8 @@ module lsu (
 
       ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY), 
         .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
-        .HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM);
+        .HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
+        .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWordM);
           
       assign ReadDataWordMuxM = LittleEndianReadDataWordM;  // from byte swapping
       assign LSUHBURST = 3'b0;