forked from Github_Repos/cvw
add im flags for compressed disass
This commit is contained in:
parent
df4419dea2
commit
a5a5b7a408
@ -1,20 +1,26 @@
|
|||||||
#--showoverrides
|
#--showoverrides
|
||||||
|
--override cpu/show_c_prefix=T
|
||||||
--override cpu/unaligned=F
|
--override cpu/unaligned=F
|
||||||
--override refRoot/cpu/mstatus_FS=1
|
--override cpu/mstatus_FS=1
|
||||||
|
|
||||||
# Enable the Imperas instruction coverage
|
# Enable the Imperas instruction coverage
|
||||||
-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
|
-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
|
||||||
-override refRoot/cpu/cv/cover=basic
|
-override refRoot/cpu/cv/cover=basic
|
||||||
-override refRoot/cpu/cv/extensions=RV32I
|
-override refRoot/cpu/cv/extensions=RV32I
|
||||||
|
|
||||||
# Add Imperas simulator application instruction tracing
|
# Add Imperas simulator application instruction tracing
|
||||||
--trace
|
--trace
|
||||||
--tracechange
|
--tracechange
|
||||||
--traceshowicount
|
--traceshowicount
|
||||||
--tracemode
|
--tracemode
|
||||||
--monitornetschange
|
--monitornetschange
|
||||||
|
|
||||||
# Turn on verbose output for Imperas simulator
|
# Turn on verbose output for Imperas simulator
|
||||||
--verbose
|
--verbose
|
||||||
|
|
||||||
# Turn on verbose output for RISCV model
|
# Turn on verbose output for RISCV model
|
||||||
--override cpu/verbose=1
|
--override cpu/verbose=1
|
||||||
|
|
||||||
# Store simulator output to logfile
|
# Store simulator output to logfile
|
||||||
--output imperas.log
|
--output imperas.log
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user