diff --git a/pipelined/regression/imperas.ic b/pipelined/regression/imperas.ic
index 8a925389..164cec22 100644
--- a/pipelined/regression/imperas.ic
+++ b/pipelined/regression/imperas.ic
@@ -1,20 +1,26 @@
 #--showoverrides
+--override cpu/show_c_prefix=T
 --override cpu/unaligned=F
---override refRoot/cpu/mstatus_FS=1
+--override cpu/mstatus_FS=1
+
 # Enable the Imperas instruction coverage
 -extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
 -override  refRoot/cpu/cv/cover=basic
 -override  refRoot/cpu/cv/extensions=RV32I
+
 # Add Imperas simulator application instruction tracing
 --trace
 --tracechange
 --traceshowicount
 --tracemode
 --monitornetschange
+
 # Turn on verbose output for Imperas simulator
 --verbose
+
 # Turn on verbose output for RISCV model
 --override  cpu/verbose=1
+
 # Store simulator output to logfile
 --output imperas.log