diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
index 6e4166b1..ad58f44f 100755
--- a/src/fpu/fctrl.sv
+++ b/src/fpu/fctrl.sv
@@ -126,18 +126,15 @@ module fctrl (
                                     3'b000:  ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj
                                     3'b001:  ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn
                                     3'b010:  ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx
-//                                    default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
                                   endcase
                       7'b00101??: case(Funct3D)
                                     3'b000:  ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin
                                     3'b001:  ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax
- //                                   default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
                                   endcase
                       7'b10100??: case(Funct3D)
                                     3'b010:  ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq
                                     3'b001:  ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt
                                     3'b000:  ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle
- //                                   default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction
                                   endcase
                       7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)          
                                                 ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass
@@ -202,9 +199,7 @@ module fctrl (
                                     5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q  q->lu
                                   endcase
                                 
-//                      default:    ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
                     endcase
-//        default:      ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
       endcase
     end
     /* verilator lint_on CASEINCOMPLETE */
@@ -333,7 +328,5 @@ module fctrl (
   flopenrc #(4)  MWCtrlReg(clk, reset, FlushW, ~StallW,
           {FRegWriteM, FResSelM, FCvtIntM},
           {FRegWriteW, FResSelW, FCvtIntW});
-  
-  //assign FCvtIntW = (FResSelW == 2'b01);
-
+ 
 endmodule
\ No newline at end of file