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added 1 tick delay to dtim flops

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bbracker 2021-03-25 02:23:30 -04:00
parent 02e924e55a
commit a3788eb218
1 changed files with 6 additions and 6 deletions
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12
wally-pipelined/src/uncore/dtim.sv
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@ -85,15 +85,15 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
generate generate
if (`XLEN == 64) begin if (`XLEN == 64) begin
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
HWADDR <= A; HWADDR <= #1 A;
HREADTim0 <= RAM[A[31:3]]; HREADTim0 <= #1 RAM[A[31:3]];
if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= HWDATA; if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA;
end end
end else begin end else begin
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
HWADDR <= A; HWADDR <= #1 A;
HREADTim0 <= RAM[A[31:2]]; HREADTim0 <= #1 RAM[A[31:2]];
if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= HWDATA; if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= #1 HWDATA;
end end
end end
endgenerate endgenerate