From a3788eb21837cf857cb70ee423433b30a1b0ebf4 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 25 Mar 2021 02:23:30 -0400 Subject: [PATCH] added 1 tick delay to dtim flops --- wally-pipelined/src/uncore/dtim.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index a5c4574e..29d938f1 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -85,15 +85,15 @@ module dtim #(parameter BASE=0, RANGE = 65535) ( generate if (`XLEN == 64) begin always_ff @(posedge HCLK) begin - HWADDR <= A; - HREADTim0 <= RAM[A[31:3]]; - if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= HWDATA; + HWADDR <= #1 A; + HREADTim0 <= #1 RAM[A[31:3]]; + if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA; end end else begin always_ff @(posedge HCLK) begin - HWADDR <= A; - HREADTim0 <= RAM[A[31:2]]; - if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= HWDATA; + HWADDR <= #1 A; + HREADTim0 <= #1 RAM[A[31:2]]; + if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= #1 HWDATA; end end endgenerate