forked from Github_Repos/cvw
everyone gets a bootram
This commit is contained in:
Noah Boorstin
parent
ced2a32d21
commit
a2b0af460e
@ -66,6 +66,8 @@
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIMBASE 32'h00000000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h00000000
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`define TIMRANGE 32'hFFFFFFFF
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`define CLINTBASE 32'h02000000
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@ -66,6 +66,8 @@
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIMBASE 32'h00000000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h000FFFFF
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`define CLINTBASE 32'h02000000
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@ -62,6 +62,8 @@
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIMBASE 32'h00000000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h0007FFFF
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`define CLINTBASE 32'h02000000
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@ -66,6 +66,8 @@
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIMBASE 32'h00000000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h0007FFFF
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`define CLINTBASE 32'h02000000
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@ -66,6 +66,8 @@
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIMBASE 32'h00000000
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`define BOOTTIMRANGE 32'h00003FFF
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h0007FFFF
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`define CLINTBASE 32'h02000000
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@ -33,9 +33,7 @@ module imem (
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/* verilator lint_off UNDRIVEN */
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logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)];
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`ifdef BOOTTIMBASE
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logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)];
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`endif
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/* verilator lint_on UNDRIVEN */
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logic [31:0] adrbits; // needs to be 32 bits to index RAM
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logic [`XLEN-1:0] rd;
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@ -46,21 +44,13 @@ module imem (
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else assign adrbits = AdrF[31:3];
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endgenerate
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`ifndef BOOTTIMBASE
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assign #2 rd = RAM[adrbits]; // word aligned
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`else
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assign #2 rd = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options
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`endif
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// hack right now for unaligned 32-bit instructions
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// eventually this will need to cause a stall like a cache miss
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// when the instruction wraps around a cache line
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// could be optimized to only stall when the instruction wrapping is 32 bits
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`ifndef BOOTTIMBASE
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assign #2 rd2 = RAM[adrbits+1][15:0];
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`else
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assign #2 rd2 = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options
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`endif
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generate
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if (`XLEN==32) begin
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assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
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@ -68,9 +58,11 @@ module imem (
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end else begin
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assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
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: (AdrF[1] ? rd[47:16] : rd[31:0]);
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`ifndef BOOTTIMBASE
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`ifndef BUSYBEAR
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assign InstrAccessFaultF = |AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE);
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`else
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// *** this is just a hack since the logic above seems scary ***
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// TODO: this should be removed when InstrAccessFaultF works with bootram also
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assign InstrAccessFaultF = 0; //busybear: for now, i know we're not doing this
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`endif
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end
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@ -64,23 +64,17 @@ module uncore (
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logic HSELTimD, HSELCLINTD, HSELGPIOD, HSELUARTD;
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logic HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART;
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logic HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART;
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`ifdef BOOTTIMBASE
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logic [`XLEN-1:0] HREADBootTim;
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logic HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim;
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logic [1:0] MemRWboottim;
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`endif
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logic UARTIntr;// *** will need to tie INTR to an interrupt handler
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// AHB Address decoder
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adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim);
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`ifdef BOOTTIMBASE
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adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim);
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`endif
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adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT);
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`ifdef GPIOBASE
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adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO);
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`endif
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adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART);
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assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported
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@ -89,15 +83,11 @@ module uncore (
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// tightly integrated memory
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dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) dtim (.*);
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`ifdef BOOTTIMBASE
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dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
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`endif
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// memory-mapped I/O peripherals
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clint clint(.HADDR(HADDR[15:0]), .*);
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`ifdef GPIOBASE
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gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts
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`endif
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uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
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.DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1),
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.RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
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@ -105,50 +95,22 @@ module uncore (
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// mux could also include external memory
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// AHB Read Multiplexer
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assign HRDATA = ({`XLEN{HSELTimD}} & HREADTim) | ({`XLEN{HSELCLINTD}} & HREADCLINT) |
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`ifdef GPIOBASE
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({`XLEN{HSELGPIOD}} & HREADGPIO) |
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`endif
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`ifdef BOOTTIMBASE
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({`XLEN{HSELBootTimD}} & HREADBootTim) |
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`endif
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({`XLEN{HSELGPIOD}} & HREADGPIO) | ({`XLEN{HSELBootTimD}} & HREADBootTim) |
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({`XLEN{HSELUARTD}} & HREADUART);
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assign HRESP = HSELTimD & HRESPTim | HSELCLINTD & HRESPCLINT |
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`ifdef GPIOBASE
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HSELGPIOD & HRESPGPIO |
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`endif
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`ifdef BOOTTIMBASE
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HSELBootTimD & HRESPBootTim |
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`endif
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HSELUARTD & HRESPUART;
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assign HREADY = HSELTimD & HREADYTim | HSELCLINTD & HREADYCLINT |
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`ifdef GPIOBASE
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HSELGPIOD & HREADYGPIO |
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`endif
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`ifdef BOOTTIMBASE
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HSELBootTimD & HREADYBootTim |
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`endif
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HSELUARTD & HREADYUART;
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assign HRESP = HSELTimD & HRESPTim | HSELCLINTD & HRESPCLINT | HSELGPIOD & HRESPGPIO |
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HSELBootTimD & HRESPBootTim | HSELUARTD & HRESPUART;
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assign HREADY = HSELTimD & HREADYTim | HSELCLINTD & HREADYCLINT | HSELGPIOD & HREADYGPIO |
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HSELBootTimD & HREADYBootTim | HSELUARTD & HREADYUART;
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// Faults
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assign DataAccessFaultM = ~(HSELTimD | HSELCLINTD |
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`ifdef GPIOBASE
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HSELGPIOD |
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`endif
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`ifdef BOOTTIMBASE
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HSELBootTimD |
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`endif
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HSELUARTD);
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assign DataAccessFaultM = ~(HSELTimD | HSELCLINTD | HSELGPIOD | HSELBootTimD | HSELUARTD);
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// Address Decoder Delay (figure 4-2 in spec)
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flopr #(1) hseltimreg(HCLK, ~HRESETn, HSELTim, HSELTimD);
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flopr #(1) hselclintreg(HCLK, ~HRESETn, HSELCLINT, HSELCLINTD);
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`ifdef GPIOBASE
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flopr #(1) hselgpioreg(HCLK, ~HRESETn, HSELGPIO, HSELGPIOD);
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`endif
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flopr #(1) hseluartreg(HCLK, ~HRESETn, HSELUART, HSELUARTD);
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`ifdef BOOTTIMBASE
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flopr #(1) hselboottimreg(HCLK, ~HRESETn, HSELBootTim, HSELBootTimD);
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`endif
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endmodule
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