From a2b0af460e807b481d72daacfeada5ce912e8cee Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 18 Mar 2021 12:35:37 -0400 Subject: [PATCH] everyone gets a bootram --- .../config/coremark/wally-config.vh | 2 + .../config/coremark_bare/wally-config.vh | 2 + wally-pipelined/config/rv32ic/wally-config.vh | 2 + wally-pipelined/config/rv64ic/wally-config.vh | 2 + .../config/rv64icfd/wally-config.vh | 2 + wally-pipelined/src/uncore/imem.sv | 14 ++---- wally-pipelined/src/uncore/uncore.sv | 50 +++---------------- 7 files changed, 19 insertions(+), 55 deletions(-) diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index 6c6484b2..95c12787 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -66,6 +66,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMBASE 32'h00000000 +`define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h00000000 `define TIMRANGE 32'hFFFFFFFF `define CLINTBASE 32'h02000000 diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index e9bd708f..320f8b8f 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -66,6 +66,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMBASE 32'h00000000 +`define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h80000000 `define TIMRANGE 32'h000FFFFF `define CLINTBASE 32'h02000000 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index e68f8416..96cf6c4f 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -62,6 +62,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMBASE 32'h00000000 +`define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h80000000 `define TIMRANGE 32'h0007FFFF `define CLINTBASE 32'h02000000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 6fa71272..f12ef7d2 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -66,6 +66,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMBASE 32'h00000000 +`define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h80000000 `define TIMRANGE 32'h0007FFFF `define CLINTBASE 32'h02000000 diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index be8d7c8a..8004f735 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -66,6 +66,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +`define BOOTTIMBASE 32'h00000000 +`define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h80000000 `define TIMRANGE 32'h0007FFFF `define CLINTBASE 32'h02000000 diff --git a/wally-pipelined/src/uncore/imem.sv b/wally-pipelined/src/uncore/imem.sv index 64f3a0d6..07eb239e 100644 --- a/wally-pipelined/src/uncore/imem.sv +++ b/wally-pipelined/src/uncore/imem.sv @@ -33,9 +33,7 @@ module imem ( /* verilator lint_off UNDRIVEN */ logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)]; - `ifdef BOOTTIMBASE logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)]; - `endif /* verilator lint_on UNDRIVEN */ logic [31:0] adrbits; // needs to be 32 bits to index RAM logic [`XLEN-1:0] rd; @@ -46,21 +44,13 @@ module imem ( else assign adrbits = AdrF[31:3]; endgenerate - `ifndef BOOTTIMBASE - assign #2 rd = RAM[adrbits]; // word aligned - `else assign #2 rd = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options - `endif // hack right now for unaligned 32-bit instructions // eventually this will need to cause a stall like a cache miss // when the instruction wraps around a cache line // could be optimized to only stall when the instruction wrapping is 32 bits - `ifndef BOOTTIMBASE - assign #2 rd2 = RAM[adrbits+1][15:0]; - `else assign #2 rd2 = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options - `endif generate if (`XLEN==32) begin assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd; @@ -68,9 +58,11 @@ module imem ( end else begin assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32]) : (AdrF[1] ? rd[47:16] : rd[31:0]); - `ifndef BOOTTIMBASE + `ifndef BUSYBEAR assign InstrAccessFaultF = |AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE); `else + // *** this is just a hack since the logic above seems scary *** + // TODO: this should be removed when InstrAccessFaultF works with bootram also assign InstrAccessFaultF = 0; //busybear: for now, i know we're not doing this `endif end diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index c068616c..6bda1d5e 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -64,23 +64,17 @@ module uncore ( logic HSELTimD, HSELCLINTD, HSELGPIOD, HSELUARTD; logic HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART; logic HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART; - `ifdef BOOTTIMBASE logic [`XLEN-1:0] HREADBootTim; logic HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim; logic [1:0] MemRWboottim; - `endif logic UARTIntr;// *** will need to tie INTR to an interrupt handler // AHB Address decoder adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim); - `ifdef BOOTTIMBASE adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim); - `endif adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT); - `ifdef GPIOBASE adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO); - `endif adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART); assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported @@ -89,15 +83,11 @@ module uncore ( // tightly integrated memory dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) dtim (.*); - `ifdef BOOTTIMBASE dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); - `endif // memory-mapped I/O peripherals clint clint(.HADDR(HADDR[15:0]), .*); - `ifdef GPIOBASE gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts - `endif uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); @@ -105,50 +95,22 @@ module uncore ( // mux could also include external memory // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELTimD}} & HREADTim) | ({`XLEN{HSELCLINTD}} & HREADCLINT) | - `ifdef GPIOBASE - ({`XLEN{HSELGPIOD}} & HREADGPIO) | - `endif - `ifdef BOOTTIMBASE - ({`XLEN{HSELBootTimD}} & HREADBootTim) | - `endif + ({`XLEN{HSELGPIOD}} & HREADGPIO) | ({`XLEN{HSELBootTimD}} & HREADBootTim) | ({`XLEN{HSELUARTD}} & HREADUART); - assign HRESP = HSELTimD & HRESPTim | HSELCLINTD & HRESPCLINT | - `ifdef GPIOBASE - HSELGPIOD & HRESPGPIO | - `endif - `ifdef BOOTTIMBASE - HSELBootTimD & HRESPBootTim | - `endif - HSELUARTD & HRESPUART; - assign HREADY = HSELTimD & HREADYTim | HSELCLINTD & HREADYCLINT | - `ifdef GPIOBASE - HSELGPIOD & HREADYGPIO | - `endif - `ifdef BOOTTIMBASE - HSELBootTimD & HREADYBootTim | - `endif - HSELUARTD & HREADYUART; + assign HRESP = HSELTimD & HRESPTim | HSELCLINTD & HRESPCLINT | HSELGPIOD & HRESPGPIO | + HSELBootTimD & HRESPBootTim | HSELUARTD & HRESPUART; + assign HREADY = HSELTimD & HREADYTim | HSELCLINTD & HREADYCLINT | HSELGPIOD & HREADYGPIO | + HSELBootTimD & HREADYBootTim | HSELUARTD & HREADYUART; // Faults - assign DataAccessFaultM = ~(HSELTimD | HSELCLINTD | - `ifdef GPIOBASE - HSELGPIOD | - `endif - `ifdef BOOTTIMBASE - HSELBootTimD | - `endif - HSELUARTD); + assign DataAccessFaultM = ~(HSELTimD | HSELCLINTD | HSELGPIOD | HSELBootTimD | HSELUARTD); // Address Decoder Delay (figure 4-2 in spec) flopr #(1) hseltimreg(HCLK, ~HRESETn, HSELTim, HSELTimD); flopr #(1) hselclintreg(HCLK, ~HRESETn, HSELCLINT, HSELCLINTD); - `ifdef GPIOBASE flopr #(1) hselgpioreg(HCLK, ~HRESETn, HSELGPIO, HSELGPIOD); - `endif flopr #(1) hseluartreg(HCLK, ~HRESETn, HSELUART, HSELUARTD); - `ifdef BOOTTIMBASE flopr #(1) hselboottimreg(HCLK, ~HRESETn, HSELBootTim, HSELBootTimD); - `endif endmodule