From 7656e3031cb7f10e8579849fbb9a1ee21914ac04 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 01:03:09 +0000 Subject: [PATCH 1/4] quit --- pipelined/config/rv64gc/wally-config.vh | 4 ++-- pipelined/testbench/testbench.sv | 20 ++++++++++++++++---- pipelined/testbench/tests.vh | 2 +- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 35b74c6d..d7ad9d3c 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -131,8 +131,8 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" +`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/shared/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index d070aa3f..e3eaf93b 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -327,11 +327,23 @@ logic [3:0] dummy; .done(DCacheFlushDone)); // initialize the branch predictor - if (`BPRED_ENABLED == 1) + if (`BPRED_ENABLED == 1) initial begin - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); - end + integer adrindex; + + // Initializing all zeroes into the branch predictor memory. + for(adrindex = 0; adrindex < 1024; adrindex++) begin + force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + end + #1; + for(adrindex = 0; adrindex < 1024; adrindex++) begin + release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; + release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end + // $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); + // $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); + end endmodule module riscvassertions; diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 49ff0ff5..dba197f5 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -962,7 +962,7 @@ string imperas32f[] = '{ "rv64i_m/I/andi-01", "6010", "rv64i_m/I/auipc-01", "2010", "rv64i_m/I/beq-01", "47010", - "rv64i_m/I/bge-01", "46010", + "rv64i_m/I/bge-01", "47010", "rv64i_m/I/bgeu-01", "56010", "rv64i_m/I/blt-01", "4d010", "rv64i_m/I/bltu-01", "57010", From e4f0f555305257fc775588c7878f7a5e29187954 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 01:04:13 +0000 Subject: [PATCH 2/4] Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature. --- pipelined/testbench/testbench.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index e3eaf93b..5aa1750d 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -341,8 +341,6 @@ logic [3:0] dummy; release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; end - // $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - // $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); end endmodule From ac44da549febd1a3c772a2bffce9202f656fd52f Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Tue, 17 May 2022 01:10:31 +0000 Subject: [PATCH 3/4] added plotting --- synthDC/ppa.py | 80 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 63 insertions(+), 17 deletions(-) diff --git a/synthDC/ppa.py b/synthDC/ppa.py index 4d165777..1eefb102 100755 --- a/synthDC/ppa.py +++ b/synthDC/ppa.py @@ -1,28 +1,37 @@ #!/usr/bin/python3 -# from msilib.schema import File +#from msilib.schema import File import subprocess from multiprocessing import Pool import csv import re -# import matplotlib.pyplot as plt -# import numpy as np +import matplotlib.pyplot as plt +import numpy as np -print("hi") -def run_command(module, width, freq): - command = "make synth DESIGN=ppa_{}_{} TECH=sky90 DRIVE=INV FREQ={} MAXOPT=1".format(module, width, freq) +def run_command(module, width, tech, freq): + command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1".format(module, width, tech, freq) subprocess.Popen(command, shell=True) -widths = ['16'] -modules = ['shifter'] -freqs = ['10'] +def deleteRedundant(LoT): + '''not working''' + synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}_{}_*" + for synth in LoT: + print(synth) + bashCommand = synthStr.format(*synth) + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) +widths = ['8'] +modules = ['add'] +freqs = ['10'] +tech = 'sky90' LoT = [] for module in modules: for width in widths: for freq in freqs: - LoT += [[module, width, freq]] + LoT += [[module, width, tech, freq]] + +deleteRedundant(LoT) pool = Pool() pool.starmap(run_command, LoT) @@ -45,13 +54,11 @@ allSynths = [] for i in range(len(linesCPL)): line = linesCPL[i] - oneSynth = [] mwm = wm.findall(line)[0][4:-4].split('_') - oneSynth += [mwm[0]] - oneSynth += [mwm[1]] - oneSynth += [f.findall(line)[0][1:-4]] - oneSynth += cpl.findall(line) - oneSynth += da.findall(linesDA[i]) + oneSynth = [mwm[0], int(mwm[1])] + oneSynth += [int(f.findall(line)[0][1:-4])] + oneSynth += [float(cpl.findall(line)[0])] + oneSynth += [float(da.findall(linesDA[i])[0])] allSynths += [oneSynth] file = open("ppaData.csv", "w") @@ -61,4 +68,43 @@ writer.writerow(['Module', 'Width', 'Target Freq', 'Delay', 'Area']) for one in allSynths: writer.writerow(one) -file.close() \ No newline at end of file +file.close() + + +def plotPPA(module, freq, var): + ''' + module: string module name + freq: int freq (GHz) + var: string 'delay' or 'area' + plots chosen variable vs width for all matching syntheses with regression + ''' + global allSynths + ind = 3 if (var == 'delay') else 4 + widths = [] + ivar = [] + for oneSynth in allSynths: + if (oneSynth[0] == module) & (oneSynth[2] == freq): + + widths += [oneSynth[1]] + ivar += [oneSynth[ind]] + + x = np.array(widths, dtype=np.int) + y = np.array(ivar, dtype=np.float) + + A = np.vstack([x, np.ones(len(x))]).T + m, c = np.linalg.lstsq(A, y, rcond=None)[0] + z = np.polyfit(x, y, 2) + p = np.poly1d(z) + + xp = np.linspace(0, 140, 200) + + _ = plt.plot(x, y, 'o', label=module, markersize=10) + _ = plt.plot(x, m*x + c, 'r', label='Linear fit') + _ = plt.plot(xp, p(xp), label='Quadratic fit') + _ = plt.legend() + _ = plt.xlabel("Width (bits)") + _ = plt.ylabel(str.title(var)) + plt.show() + + +plotPPA('add', 5000, 'delay') \ No newline at end of file From d34a942eb278e46d1f9662f39facb6fe595a128c Mon Sep 17 00:00:00 2001 From: mmasserfrye Date: Tue, 17 May 2022 01:11:43 +0000 Subject: [PATCH 4/4] added 8 and 128 bit versions, adjusted alu --- pipelined/src/ppa/ppa.sv | 80 +++++++++++++++++++++++++++++++++++----- 1 file changed, 70 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 01e06bb7..03b004f6 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -3,6 +3,14 @@ // & mmasserfrye@hmc.edu // Measure PPA of various building blocks +module ppa_comparator_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -27,6 +35,14 @@ module ppa_comparator_64 #(parameter WIDTH=64) ( ppa_comparator #(WIDTH) comp (.*); endmodule +module ppa_comparator_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + module ppa_comparator #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, input logic sgnd, @@ -45,6 +61,13 @@ module ppa_comparator #(parameter WIDTH=16) ( assign flags = {eq, lt}; endmodule +module ppa_add_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + module ppa_add_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] y); @@ -66,6 +89,19 @@ module ppa_add_64 #(parameter WIDTH=64) ( assign y = a + b; endmodule +module ppa_add_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_mult_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_mult_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH*2-1:0] y); //is this right width @@ -84,6 +120,12 @@ module ppa_mult_64 #(parameter WIDTH=64) ( assign y = a * b; endmodule +module ppa_mult_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + module ppa_alu_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, B, input logic [2:0] ALUControl, @@ -180,6 +222,15 @@ module ppa_shiftleft #(parameter WIDTH=32) ( assign y = a << amt; endmodule +module ppa_shifter_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter_16 #(parameter WIDTH=16) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -207,6 +258,15 @@ module ppa_shifter_64 #(parameter WIDTH=64) ( ppa_shifter #(WIDTH) sh (.*); endmodule +module ppa_shifter_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + ppa_shifter #(WIDTH) sh (.*); +endmodule + module ppa_shifter #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, input logic [$clog2(WIDTH)-1:0] Amt, @@ -221,14 +281,7 @@ module ppa_shifter #(parameter WIDTH=32) ( // For RV64, 32 and 64-bit shifts are needed, with sign extension. // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (WIDTH==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 + if (WIDTH == 64) begin:shifter // RV64 fix what about 128 always_comb // funnel mux if (W64) begin // 32-bit shifts if (Right) @@ -241,8 +294,15 @@ module ppa_shifter #(parameter WIDTH=32) ( else z = {63'b0, A}; else z = {A, 63'b0}; end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift - end + end else begin:shifter // RV32, + always_comb // funnel mux + if (Right) + if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + else z = {{WIDTH-1{1'b0}}, A}; + else z = {A, {WIDTH-1{1'b0}}}; + assign amttrunc = Amt; // shift amount + end + assign amttrunc = (W64 & WIDTH==64) ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift fix // opposite offset for right shfits assign offset = Right ? amttrunc : ~amttrunc;