From 9f25b53b362fa8870633a503e09383f2e0abf3da Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 17:57:05 -0600
Subject: [PATCH] Fixed bug in basic gshare implementation.  Should be a better
 comparison to the speculative versions now.

---
 src/ifu/bpred/gshare.sv      |  4 ++--
 src/ifu/bpred/gshare_copy.sv | 20 +++++++++++---------
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index fde1a082..4cffbf93 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -48,8 +48,8 @@ module gshare #(parameter k = 10) (
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
-  assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
diff --git a/src/ifu/bpred/gshare_copy.sv b/src/ifu/bpred/gshare_copy.sv
index 119056c8..d73bce20 100644
--- a/src/ifu/bpred/gshare_copy.sv
+++ b/src/ifu/bpred/gshare_copy.sv
@@ -31,16 +31,16 @@
 module gshare_copy #(parameter k = 10) (
   input logic             clk,
   input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, 
-  input logic             FlushD, FlushE, FlushM,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCE,
+  input logic [`XLEN-1:0] PCNextF, PCM,
   input logic             BranchInstrE, BranchInstrM, PCSrcE
 );
 
-  logic [k-1:0]            IndexNextF, IndexE;
+  logic [k-1:0]            IndexNextF, IndexM;
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
@@ -48,16 +48,16 @@ module gshare_copy #(parameter k = 10) (
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
-  assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexNextF = GHRNext ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexM = GHR ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(DirPredictionF),
-    .wa2(IndexE),
-    .wd2(NewDirPredictionE),
-    .we2(BranchInstrE & ~StallM & ~FlushM),
+    .wa2(IndexM),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallW & ~FlushW),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -72,9 +72,11 @@ module gshare_copy #(parameter k = 10) (
   flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
     
+/* -----\/----- EXCLUDED -----\/-----
   flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
   flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
   flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+ -----/\----- EXCLUDED -----/\----- */
 
 
 endmodule