diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc
index 6b0a0363..b21b1cc5 100644
--- a/fpga/constraints/constraints.xdc
+++ b/fpga/constraints/constraints.xdc
@@ -35,12 +35,14 @@ set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_por
 
 
 ##### UART #####
-set_property PACKAGE_PIN AW25 [get_ports UARTSin]
-set_property PACKAGE_PIN BB21 [get_ports UARTSout]
+#set_property PACKAGE_PIN AW25 [get_ports UARTSin]
+set_property PACKAGE_PIN R29 [get_ports UARTSin]
+#set_property PACKAGE_PIN BB21 [get_ports UARTSout]
+set_property PACKAGE_PIN M31 [get_ports UARTSout]
 set_max_delay -from [get_ports UARTSin] 10.000
 set_max_delay -to [get_ports UARTSout] 10.000
-set_property IOSTANDARD LVCMOS18 [get_ports UARTSin]
-set_property IOSTANDARD LVCMOS18 [get_ports UARTSout]
+set_property IOSTANDARD LVCMOS12 [get_ports UARTSin]
+set_property IOSTANDARD LVCMOS12 [get_ports UARTSout]
 set_property DRIVE 6 [get_ports UARTSout]
 set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
 set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]