From 99423993a9e7537b7e9c3902f93e35b0a08c77e7 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 4 May 2022 23:00:17 +0000 Subject: [PATCH] added explicit clears to mstatus.mie --- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S | 4 ++-- .../riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S | 2 ++ .../rv32i_m/privilege/src/WALLY-status-sie-01.S | 2 ++ .../riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S | 2 ++ .../riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S | 2 ++ .../riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S | 2 ++ .../riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S | 2 +- .../riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S | 2 ++ .../rv64i_m/privilege/src/WALLY-status-sie-01.S | 2 ++ .../riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S | 2 ++ .../riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S | 2 ++ .../riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S | 4 +++- 12 files changed, 24 insertions(+), 4 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S index 512adbca..5c0f70b2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S @@ -32,12 +32,12 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits. li x28, 0x8 -csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode +csrs mstatus, x28 // set sstatus.MIE bit to 1 WRITE_READ_CSR mie, 0xFFF // cause traps, ensuring that we DONT go through the vectored part of the trap handler -jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack +jal cause_m_time_interrupt // only cause one interrupt because we just want to test the status stack END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S index 8f8b354a..c3af8142 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S @@ -31,6 +31,8 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S index fbdfc179..740e1b04 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S @@ -32,6 +32,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts. li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S index 21d031d8..03dd7756 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S @@ -34,6 +34,8 @@ TRAP_HANDLER s, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, whi li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR mie, 0xFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 061b8de7..82787516 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -36,6 +36,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie. GOTO_S_MODE diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S index b97f7a15..90d4fd39 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S @@ -36,6 +36,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR mie, 0xFFFF GOTO_U_MODE diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S index 5c9a9ab0..54385756 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S @@ -32,7 +32,7 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva TRAP_HANDLER m, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, while turning on recording of mstatus bits. li x28, 0x8 -csrs mstatus, x28 // set sstatus.MIE bit to 1 +csrs mstatus, x28 // set mstatus.MIE bit to 1 WRITE_READ_CSR mie, 0xFFF // cause traps, ensuring that we DONT go through the vectored part of the trap handler diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S index 0a0e869b..cc681af2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S @@ -31,6 +31,8 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S index aecca989..a35e85b4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S @@ -32,6 +32,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts. li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S index c5b2dcd0..100834e3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S @@ -34,6 +34,8 @@ TRAP_HANDLER s, VECTORED=0, EXT_SIGNATURE=1 // turn off vectored interrupts, whi li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR mie, 0xFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index 8e096a2e..147ad893 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -36,6 +36,8 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well li x28, 0x2 csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie. GOTO_S_MODE diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S index 5310b2dc..bc07738c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -35,7 +35,9 @@ TRAP_HANDLER s, EXT_SIGNATURE=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg li x28, 0x2 -csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to +csrs sstatus, x28 // set sstatus.SIE bit to 1 +li x28, 0x8 +csrc mstatus, x28 // clear mstatus.MIE bit WRITE_READ_CSR mie, 0xFFFF GOTO_U_MODE