fix checkpointing so that it can find the synchronized reset signal

wally-pipelined/testbench/testbench-linux.sv

@@ -48,7 +48,7 @@ module testbench();
   ///////////////////////////////////////////////////////////////////////////////
   ////////////////////////////////// HARDWARE ///////////////////////////////////
   ///////////////////////////////////////////////////////////////////////////////
-  logic clk, reset, reset_ext; 
+  logic clk, reset_ext; 
   initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
   always begin clk <= 1; # 5; clk <= 0; # 5; end
 
@@ -85,6 +85,9 @@ module testbench();
                         .UARTSin, .UARTSout,
 			.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
 
+  logic reset;
+  assign reset = dut.reset;
+
   // Write Back stage signals not needed by Wally itself 
   parameter nop = 'h13;
   logic [`XLEN-1:0] PCW;