From 979580b1e73426fe23ecba1477d2eab7ffc3c083 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Tue, 7 Dec 2021 13:12:06 -0800
Subject: [PATCH] fix checkpointing so that it can find the synchronized reset
 signal

---
 wally-pipelined/testbench/testbench-linux.sv | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index 50559b9d..a757e4f7 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -48,7 +48,7 @@ module testbench();
   ///////////////////////////////////////////////////////////////////////////////
   ////////////////////////////////// HARDWARE ///////////////////////////////////
   ///////////////////////////////////////////////////////////////////////////////
-  logic clk, reset, reset_ext; 
+  logic clk, reset_ext; 
   initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
   always begin clk <= 1; # 5; clk <= 0; # 5; end
 
@@ -85,6 +85,9 @@ module testbench();
                         .UARTSin, .UARTSout,
 			.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
 
+  logic reset;
+  assign reset = dut.reset;
+
   // Write Back stage signals not needed by Wally itself 
   parameter nop = 'h13;
   logic [`XLEN-1:0] PCW;