forked from Github_Repos/cvw
fix checkpointing so that it can find the synchronized reset signal
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parent
302bc56646
commit
979580b1e7
@ -48,7 +48,7 @@ module testbench();
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////// HARDWARE ///////////////////////////////////
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////////////////////////////////// HARDWARE ///////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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logic clk, reset, reset_ext;
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logic clk, reset_ext;
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initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
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initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
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always begin clk <= 1; # 5; clk <= 0; # 5; end
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always begin clk <= 1; # 5; clk <= 0; # 5; end
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@ -85,6 +85,9 @@ module testbench();
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.UARTSin, .UARTSout,
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.UARTSin, .UARTSout,
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.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
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.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
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logic reset;
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assign reset = dut.reset;
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// Write Back stage signals not needed by Wally itself
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// Write Back stage signals not needed by Wally itself
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parameter nop = 'h13;
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parameter nop = 'h13;
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logic [`XLEN-1:0] PCW;
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logic [`XLEN-1:0] PCW;
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