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updated pipeline tests

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This commit is contained in:
Shriya Nadgauda 2021-05-03 22:07:36 -04:00
parent a4dad3403e
commit 968994c04a
4 changed files with 259 additions and 79 deletions
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2
wally-pipelined/config/rv32ic/wally-config.vh
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@ -69,7 +69,7 @@
`define BOOTTIMBASE 32'h00000000 `define BOOTTIMBASE 32'h00000000
`define BOOTTIMRANGE 32'h00003FFF `define BOOTTIMRANGE 32'h00003FFF
`define TIMBASE 32'h80000000 `define TIMBASE 32'h80000000
`define TIMRANGE 32'h0007FFFF `define TIMRANGE 32'h0FFFFFFF
`define CLINTBASE 32'h02000000 `define CLINTBASE 32'h02000000
`define CLINTRANGE 32'h0000FFFF `define CLINTRANGE 32'h0000FFFF
`define GPIOBASE 32'h10012000 `define GPIOBASE 32'h10012000

2
wally-pipelined/config/rv64ic/wally-config.vh
View File

@ -73,7 +73,7 @@
`define BOOTTIMBASE 32'h00000000 `define BOOTTIMBASE 32'h00000000
`define BOOTTIMRANGE 32'h00003FFF `define BOOTTIMRANGE 32'h00003FFF
`define TIMBASE 32'h80000000 `define TIMBASE 32'h80000000
`define TIMRANGE 32'h0007FFFF `define TIMRANGE 32'h0FFFFFFF
`define CLINTBASE 32'h02000000 `define CLINTBASE 32'h02000000
`define CLINTRANGE 32'h0000FFFF `define CLINTRANGE 32'h0000FFFF
`define GPIOBASE 32'h10012000 `define GPIOBASE 32'h10012000

37
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -34,9 +34,11 @@ module testbench();
logic clk; logic clk;
logic reset; logic reset;
parameter SIGNATURESIZE = 5000000;
int test, i, errors, totalerrors; int test, i, errors, totalerrors;
logic [31:0] sig32[0:10000]; logic [31:0] sig32[0:SIGNATURESIZE];
logic [`XLEN-1:0] signature[0:10000]; logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
logic [`XLEN-1:0] testadr; logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW; logic [31:0] InstrW;
@ -115,6 +117,7 @@ module testbench();
}; };
string tests64i[] = '{ string tests64i[] = '{
"rv64i/WALLY-PIPELINE-100K", "f7ff0",
"rv64i/I-ADD-01", "3000", "rv64i/I-ADD-01", "3000",
"rv64i/I-ADDI-01", "3000", "rv64i/I-ADDI-01", "3000",
"rv64i/I-ADDIW-01", "3000", "rv64i/I-ADDIW-01", "3000",
@ -260,6 +263,7 @@ module testbench();
}; };
string tests32i[] = { string tests32i[] = {
"rv32i/WALLY-PIPELINE-100K", "10a800",
"rv32i/I-ADD-01", "2000", "rv32i/I-ADD-01", "2000",
"rv32i/I-ADDI-01","2000", "rv32i/I-ADDI-01","2000",
"rv32i/I-AND-01","2000", "rv32i/I-AND-01","2000",
@ -275,7 +279,7 @@ module testbench();
"rv32i/I-EBREAK-01","2000", "rv32i/I-EBREAK-01","2000",
"rv32i/I-ECALL-01","2000", "rv32i/I-ECALL-01","2000",
"rv32i/I-ENDIANESS-01","2010", "rv32i/I-ENDIANESS-01","2010",
"rv32i/I-IO-01","2030", "rv32i/I-IO-01","2030rv",
"rv32i/I-JAL-01","3000", "rv32i/I-JAL-01","3000",
"rv32i/I-JALR-01","3000", "rv32i/I-JALR-01","3000",
"rv32i/I-LB-01","3020", "rv32i/I-LB-01","3020",
@ -334,8 +338,7 @@ module testbench();
"rv32i/WALLY-CSRRC", "4000", "rv32i/WALLY-CSRRC", "4000",
"rv32i/WALLY-CSRRWI", "3000", "rv32i/WALLY-CSRRWI", "3000",
"rv32i/WALLY-CSRRSI", "3000", "rv32i/WALLY-CSRRSI", "3000",
"rv32i/WALLY-CSRRCI", "3000", "rv32i/WALLY-CSRRCI", "3000"
"rv32i/WALLY-PIPELINE", "1a800"
}; };
string testsBP64[] = '{ string testsBP64[] = '{
@ -358,16 +361,16 @@ module testbench();
}; };
string tests32p[] = '{ string tests32p[] = '{
"rv32p/WALLY-MCAUSE", "2000", // "rv32p/WALLY-MCAUSE", "2000",
"rv32p/WALLY-SCAUSE", "2000", // "rv32p/WALLY-SCAUSE", "2000",
"rv32p/WALLY-MEPC", "5000", // "rv32p/WALLY-MEPC", "5000",
"rv32p/WALLY-SEPC", "4000", // "rv32p/WALLY-SEPC", "4000",
"rv32p/WALLY-MTVAL", "5000", // "rv32p/WALLY-MTVAL", "5000",
"rv32p/WALLY-STVAL", "4000", // "rv32p/WALLY-STVAL", "4000",
"rv32p/WALLY-MARCHID", "4000", // "rv32p/WALLY-MARCHID", "4000",
"rv32p/WALLY-MIMPID", "4000", // "rv32p/WALLY-MIMPID", "4000",
"rv32p/WALLY-MHARTID", "4000", // "rv32p/WALLY-MHARTID", "4000",
"rv32p/WALLY-MVENDORID", "4000" // "rv32p/WALLY-MVENDORID", "4000"
}; };
string tests64periph[] = '{ string tests64periph[] = '{
@ -499,7 +502,7 @@ module testbench();
$display("Code ended with ecall with gp = 1"); $display("Code ended with ecall with gp = 1");
#60; // give time for instructions in pipeline to finish #60; // give time for instructions in pipeline to finish
// clear signature to prevent contamination from previous tests // clear signature to prevent contamination from previous tests
for(i=0; i<10000; i=i+1) begin for(i=0; i<SIGNATURESIZE; i=i+1) begin
sig32[i] = 'bx; sig32[i] = 'bx;
end end
@ -507,7 +510,7 @@ module testbench();
signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"}; signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
$readmemh(signame, sig32); $readmemh(signame, sig32);
i = 0; i = 0;
while (i < 10000) begin while (i < SIGNATURESIZE) begin
if (`XLEN == 32) begin if (`XLEN == 32) begin
signature[i] = sig32[i]; signature[i] = sig32[i];
i = i+1; i = i+1;

297
wally-pipelined/testgen/testgen-PIPELINE.py
View File

@ -513,7 +513,7 @@ class RegFile():
for immutableRegKey, immutableRegVal in immutableRegsDict.items(): for immutableRegKey, immutableRegVal in immutableRegsDict.items():
self.regs[immutableRegKey].setValue(newValue = immutableRegVal, signed = 1) self.regs[immutableRegKey].setValue(newValue = immutableRegVal, signed = 1)
self.immutableRegsList.append(immutableRegKey) self.immutableRegsList.append(immutableRegKey)
def getRandReg(self): def getRandReg(self):
reg = randint(1, len(self.regs)-1) reg = randint(1, len(self.regs)-1)
while(reg in self.immutableRegsList): while(reg in self.immutableRegsList):
@ -584,10 +584,7 @@ class Memory():
if addr not in self.memDict.keys(): if addr not in self.memDict.keys():
errStr = 'Tried to read from uninitialized address: {}'.format(addr) errStr = 'Tried to read from uninitialized address: {}'.format(addr)
raise ReadFromUninitializedMemoryException(errStr) raise ReadFromUninitializedMemoryException(errStr)
# # get a random number of grandularity
# self.memDict[addr] = self.genRandMemoryValue()
# get value from memory
# print(self.memDict.items())
val = self.memDict[addr] val = self.memDict[addr]
if granularity == GRANULARITY.WORD: if granularity == GRANULARITY.WORD:
val = val val = val
@ -638,6 +635,10 @@ class TestGen():
self.imperasPath = imperasPath + instrSet.lower() + '/' self.imperasPath = imperasPath + instrSet.lower() + '/'
self.exportTestName = 'PIPELINE' self.exportTestName = 'PIPELINE'
if (self.numInstr == 100000):
self.exportTestName += "-100K"
elif (self.numInstr == 1000000):
self.exportTestName += "-1M"
self.basename = 'WALLY-'+ self.exportTestName self.basename = 'WALLY-'+ self.exportTestName
self.fname = self.imperasPath + "src/" + self.basename + ".S" self.fname = self.imperasPath + "src/" + self.basename + ".S"
self.refname = self.imperasPath + "references/" + self.basename + ".reference_output" self.refname = self.imperasPath + "references/" + self.basename + ".reference_output"
@ -647,9 +648,9 @@ class TestGen():
reg6 = self.model.regFile.regs[6] reg6 = self.model.regFile.regs[6]
out = [Instr.issue(model = self.model, instrName = "sw", rs2 = reg, imm = imm, rs1 = reg6)] out = [Instr.issue(model = self.model, instrName = "sw", rs2 = reg, imm = imm, rs1 = reg6)]
self.model.resultImmediateCounter += 4 self.model.resultImmediateCounter += 4
if (self.model.resultImmediateCounter == 2044): if (self.model.resultImmediateCounter == 2040):
# Reset # Reset
imm2 = Immediate.setImm12(xlen = self.xlen, value = 2044) imm2 = Immediate.setImm12(xlen = self.xlen, value = 2040)
reg6.setImmutable(False) reg6.setImmutable(False)
wreset = Instr.issue(model = self.model, instrName = "addi", rd = reg6, imm = imm2, rs1 = reg6) wreset = Instr.issue(model = self.model, instrName = "addi", rd = reg6, imm = imm2, rs1 = reg6)
reg6.setImmutable(True) reg6.setImmutable(True)
@ -928,14 +929,20 @@ class TestGen():
instructions = [] instructions = []
rd = self.model.regFile.getRandReg() rd = self.model.regFile.getRandReg()
memVal = self.model.memoryImmediateCounter
reg1 = self.model.regFile.regs[7] reg1 = self.model.regFile.regs[7]
memVal = self.model.memoryImmediateCounter
self.model.memoryImmediateCounter += 4 self.model.memoryImmediateCounter += 4
if (self.model.memoryImmediateCounter == 2044): if instr == "ld":
if ((memVal + reg1.getValueUnsigned()) % 8) != 0:
memVal -= 4
self.model.memoryImmediateCounter -= 4 # we haven't read from a new location
if (self.model.memoryImmediateCounter == 2040):
self.model.memoryImmediateCounter = 0 self.model.memoryImmediateCounter = 0
immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2044) immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040)
instructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = reg1, rs1 = reg1, imm = immMem)) instructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = reg1, rs1 = reg1, imm = immMem))
@ -1062,19 +1069,19 @@ class TestGen():
rs1 = self.model.regFile.getRandReg() rs1 = self.model.regFile.getRandReg()
while (rs1 == reg_pc): while (rs1 == reg_pc):
rs1 = self.model.regFile.getRandReg() rs1 = self.model.regFile.getRandReg()
# TODO fix the value of rs1 - should be pc location of "1f"
rs1.setValue(newValue = 0)
imm = Immediate.setImm12(xlen = self.model.xlen, value = 0) imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
jumpDestVal = self.model.pc.value + numInstr * 4 + 8 instructions.append('la {}, {}'.format(rs1.regName , "1f"))
generatedInstructions.append('li {}, MASK_XLEN({})'.format(rs1.regName ,jumpDestVal)) self.model.pc += 8
self.model.pc += 8
newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm, dir = "f") newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm)
instructions.append(newInstr) instructions.append(newInstr)
# add random alu instructions after jumping before jump point # add random alu instructions after jumping before jump point
reg_check = self.model.regFile.getRandReg() reg_check = self.model.regFile.getRandReg()
for i in range(0, numInstr): for i in range(0, numInstr):
@ -1086,6 +1093,9 @@ class TestGen():
r2 = self.model.regFile.getRandReg() r2 = self.model.regFile.getRandReg()
instructions.append(Instr.issue(model = self.model, instrName = "and", rd = rd, rs1 = r1, rs2 = r2)) instructions.append(Instr.issue(model = self.model, instrName = "and", rd = rd, rs1 = r1, rs2 = r2))
instructions.append("1:")
self.model.pc += 4
#make sure jump was taken #make sure jump was taken
check_instr = self.genTestInstr(reg_check) check_instr = self.genTestInstr(reg_check)
for check in check_instr: for check in check_instr:
@ -1106,6 +1116,8 @@ class TestGen():
instructions.append(newInstr) instructions.append(newInstr)
# instructions.append("jal x" + reg1 + ", 1f") # instructions.append("jal x" + reg1 + ", 1f")
instructions.append("2:")
self.model.pc += 4
newInstr = Instr.issue(model = self.model, instrName='jal', rd = reg2, label = label3, dir = "f") newInstr = Instr.issue(model = self.model, instrName='jal', rd = reg2, label = label3, dir = "f")
instructions.append(newInstr) instructions.append(newInstr)
@ -1121,40 +1133,47 @@ class TestGen():
imm = Immediate.setImm12(xlen = self.model.xlen, value = 0) imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
generatedInstructions.append('li {}, MASK_XLEN({})'.format(rs1.regName ,jumpDestVal)) instructions.append('la {}, {}'.format(rs1.regName ,"2b"))
self.model.pc += 8 self.model.pc += 8
rs1 = self.model.regFile.regs[0] rs1.setValue(newValue = 0) #TODO: this value is wrong, should be address of label
imm = Immediate.setImm12(xlen = self.model.xlen, value = jumpDestVal) imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
numInstr = np.random.randint(0,6) numInstr = np.random.randint(0,6)
for i in range(0, numInstr): for i in range(0, numInstr):
rd = self.model.regFile.getRandReg() rd = self.model.regFile.getRandReg()
while(rd == rs1) or (rd == reg_pc):
rd = self.model.regFile.getRandReg()
r1 = self.model.regFile.getRandReg() r1 = self.model.regFile.getRandReg()
r2 = self.model.regFile.getRandReg() r2 = self.model.regFile.getRandReg()
instructions.append(Instr.issue(model = self.model, instrName = 'and', rd = rd, rs1 = r1, rs2 = r2)) instructions.append(Instr.issue(model = self.model, instrName = 'and', rd = rd, rs1 = r1, rs2 = r2))
#test case here #test case here
newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg2, rs1 = rs1, imm = imm, dir = "b") newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm)
instructions.append(newInstr) instructions.append(newInstr)
# instructions.append("jal x" + reg2 + ", 2b") # instructions.append("jal x" + reg2 + ", 2b")
instructions.append("3:") instructions.append("3:")
self.model.pc += 4 self.model.pc += 4
check_instr = self.genTestInstr(reg1) check_instr = self.genTestInstr(reg1)
for check in check_instr:
instructions.append(check)
check_instr = self.genTestInstr(reg_pc)
for check in check_instr: for check in check_instr:
instructions.append(check) instructions.append(check)
# jump to 1 # jump to 1
# #2
# jump to 3 # jump to 3
# #1 # #1
# junk instructions # junk instructions
# ... # ...
# ... # ...
# test instruction # test instruction to 2
# #3 # #3
# check answer from 1 # check answer from 1
return instructions return instructions
@ -1226,17 +1245,23 @@ class TestGen():
elif randInstr in InstrTypes['I']: elif randInstr in InstrTypes['I']:
if randInstr == "jalr": if randInstr == "jalr":
# newInstr = self.jumpRInstruction(instr = randInstr) newInstr = self.jumpRInstruction(instr = randInstr)
# for i in newInstr: for i in newInstr:
# generatedInstructions.append(i) generatedInstructions.append(i)
continue
# memory instruction # memory instruction
elif randInstr[0] == 'l': elif randInstr[0] == 'l':
rd = self.model.regFile.getRandReg()
rs1 = self.model.regFile.regs[7] rs1 = self.model.regFile.regs[7]
memLocation = list(self.model.memory.memDict.keys())[randint(0, len(self.model.memory.memDict.keys()) -1)]
memLocation = list(self.model.memory.memDict.keys())[randint(0, len(self.model.memory.memDict.keys()) -1)]
if randInstr == "ld":
if ((memLocation + rs1.getValueUnsigned()) % 8) != 0:
if (memLocation != 0):
memLocation -=4
else:
memLocation = 4
rd = self.model.regFile.getRandReg()
imm12 = Immediate.setImm12(xlen = self.model.xlen, value = memLocation) imm12 = Immediate.setImm12(xlen = self.model.xlen, value = memLocation)
instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, imm = imm12) instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, imm = imm12)
generatedInstructions.append(instr) generatedInstructions.append(instr)
@ -1257,13 +1282,20 @@ class TestGen():
generatedInstructions.append(testInstr) generatedInstructions.append(testInstr)
elif randInstr in InstrTypes['S']: elif randInstr in InstrTypes['S']:
rs2 = self.model.regFile.getRandReg()
rs1 = self.model.regFile.regs[7] rs1 = self.model.regFile.regs[7]
immValue = self.model.memoryImmediateCounter immValue = self.model.memoryImmediateCounter
self.model.memoryImmediateCounter += 4 self.model.memoryImmediateCounter += 4
immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2044) if randInstr == 'Sd':
if (self.model.memoryImmediateCounter == 2044): if ((immValue + rs1.getValueUnsigned()) % 8) != 0:
immValue -= 4
self.model.memoryImmediateCounter -= 4 #haven't put a value in a new mem locatoin
rs2 = self.model.regFile.getRandReg()
immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040)
if (self.model.memoryImmediateCounter == 2040):
self.model.memoryImmediateCounter = 0 self.model.memoryImmediateCounter = 0
generatedInstructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = rs1, rs1 = rs1, imm = immMem)) generatedInstructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = rs1, rs1 = rs1, imm = immMem))
@ -1331,7 +1363,10 @@ class TestGen():
hexVal = int(self.model.memory.memDict[memLoc],2) hexVal = int(self.model.memory.memDict[memLoc],2)
hexDigitSize = self.model.xlen / 4 hexDigitSize = self.model.xlen / 4
formattedStr = '0x{0:0{1}x}'.format(hexVal, hexDigitSize) formattedStr = '0x{0:0{1}x}'.format(hexVal, hexDigitSize)
asmFile.write('\t.word {}\n'.format(formattedStr)) if self.model.xlen == 64:
asmFile.write('\t.dword {}\n'.format(formattedStr))
else:
asmFile.write('\t.word {}\n'.format(formattedStr))
lineNum += 1 lineNum += 1
asmFile.write("\n") asmFile.write("\n")
@ -1685,6 +1720,148 @@ class Instr():
return 'jal {}, {}{}'.format(rd.getRegName(), label.name, dir) return 'jal {}, {}{}'.format(rd.getRegName(), label.name, dir)
###################################################################################################
# RV 64I
###################################################################################################
#TODO These may not keep the internal model consistent. You have been warned...sorry lol
@classmethod
def Instr_ld(self, model, rd = None, rs1 = None, imm = None):
addr = imm.getDecValue()
rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD), \
resultNumBits = model.xlen))
model.pc += 4
return 'ld {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
@classmethod
def Instr_lwu(self, model, rd = None, rs1 = None, imm = None):
addr = imm.getDecValue()
rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \
resultNumBits = model.xlen))
model.pc += 4
return 'lwu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
@classmethod
def Instr_addiw(self, model, rd = None, rs1 = None, imm = None):
newValue = rs1.getDecValue() + imm.getDecValue()
newValueBin = 0
if newValue > 0:
newValueBin = bin(newValue)[2:]
elif newValue == 0:
newValueBin = "0" * model.xlen
else:
newValueBin = bin(newValue)[3:]
newValueBinTrunk = newValueBin[-model.xlen:]
rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
model.pc += 4
return 'addiw {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
@classmethod
def Instr_slliw(self, model, rd = None, rs1 = None, imm = None):
bits = rs1.bits
immBits = imm.bits[-5:]
immShift = int(immBits, 2)
shifted = bits[-(len(bits) - immShift):]
shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
rd.setValue(newValue = shiftedExt, signed = 1)
model.pc += 4
return 'slliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
@classmethod
def Instr_srliw(self, model, rd = None, rs1 = None, imm = None):
bits = rs1.bits
immBits = imm.bits[-5:]
immShift = int(immBits, 2)
shifted = bits[0:len(bits) - immShift]
extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
rd.setBits(newBits = extShifted, signed = 1)
model.pc += 4
return 'srliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
@classmethod
def Instr_sraiw(self, model, rd = None, rs1 = None, imm = None):
bits = rs1.bits
immBits = imm.bits[-5:]
immShift = int(immBits, 2)
shifted = bits[0:len(bits) - immShift]
extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
rd.setBits(newBits = extShifted, signed = 1)
model.pc += 4
return 'sraiw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
@classmethod
def Instr_Sd(self, model, rs1 = None, rs2 = None, imm = None):
addr = imm.getDecValue()
model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD)
model.pc += 4
return 'Sd {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName())
@classmethod
def Instr_addw(self, model, rd = None, rs1 = None, rs2 = None):
newValue = rs1.getDecValue() + rs2.getDecValue()
newValueBin = 0
if newValue > 0:
newValueBin = bin(newValue)[2:]
elif newValue == 0:
newValueBin = "0" * model.xlen
else:
newValueBin = bin(newValue)[3:]
newValueBinTrunk = newValueBin[-model.xlen:]
rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
model.pc += 4
return 'addw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
@classmethod
def Instr_subw(self, model, rd = None, rs1 = None, rs2 = None):
newValue = rs1.getDecValue() - rs2.getDecValue()
newValueBin = 0
if newValue > 0:
newValueBin = bin(newValue)[2:]
elif newValue == 0:
newValueBin = "0" * model.xlen
else:
newValueBin = bin(newValue)[3:]
newValueBinTrunk = newValueBin[-model.xlen:]
rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
model.pc += 4
return 'subw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
@classmethod
def Instr_sllw(self, model, rd = None, rs1 = None, rs2 = None):
bits = rs1.bits
rs2Bin = rs2.bits[-5:]
rs2Shift = int(rs2Bin,2)
shifted = bits[-(len(bits) - rs2Shift):]
shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
rd.setValue(newValue = shiftedExt, signed = 1)
model.pc += 4
return 'sllw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
@classmethod
def Instr_srlw(self, model, rd = None, rs1 = None, rs2 = None):
bits = rs1.bits
rs2Bin = rs2.bits[-5:]
rs2Shift = int(rs2Bin,2)
shifted = bits[0:len(bits) - rs2Shift]
extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
rd.setBits(newBits = extShifted, signed = 1)
model.pc += 4
return 'srlw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
@classmethod
def Instr_sraw(self, model, rd = None, rs1 = None, rs2 = None):
bits = rs1.bits
rs2Bin = rs2.bits[-5:]
rs2Shift = int(rs2Bin,2)
shifted = bits[0:len(bits) - rs2Shift]
extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
rd.setBits(newBits = extShifted, signed = 1)
model.pc += 4
return 'sraw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
################################################################################################### ###################################################################################################
# Global Constants # Global Constants
################################################################################################### ###################################################################################################
@ -1693,7 +1870,7 @@ GRANULARITY = Enum('granularity', ['WORD', 'HALFWORD', 'BYTE'])
INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \ INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \
'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \ 'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \
'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \ 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \
'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal'], \ 'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal', 'jalr'], \
'RV64I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \ 'RV64I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \
'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \ 'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \
'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \ 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \
@ -1703,9 +1880,11 @@ INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti',
} }
InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and'], \ InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', \
'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr'], \ 'addw', 'subw', 'sllw', 'srlw', 'sraw'], \
'S' : ['sw', 'sh', 'sb'], \ 'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr', \
'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw'], \
'S' : ['sw', 'sh', 'sb', 'Sd'], \
'B' : ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu'], \ 'B' : ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu'], \
'U' : ['lui', 'auipc'], \ 'U' : ['lui', 'auipc'], \
'J' : ['jal'], \ 'J' : ['jal'], \
@ -1714,27 +1893,25 @@ InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra',
# Main Body # Main Body
################################################################################################### ###################################################################################################
XLEN = ['32'] XLEN = ['32', '64']
INSTRUCTION_TYPE = ['I'] INSTRUCTION_TYPE = ['I']
NUMINSTR = 70000 NUMINSTR = [100000, 1000000]
IMPERASPATH = "../../imperas-riscv-tests/riscv-test-suite/" IMPERASPATH = "../../imperas-riscv-tests/riscv-test-suite/"
seed(42) seed(42)
np.random.seed(42) np.random.seed(42)
for xlen in XLEN: for num_instructions in NUMINSTR:
memInit = {} for xlen in XLEN:
for i in range(0, 400, 4): memInit = {}
val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1) for i in range(0, 400, 4):
memInit[i] = val val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1)
for instrType in INSTRUCTION_TYPE: memInit[i] = val
instrSet = 'RV' + xlen + instrType for instrType in INSTRUCTION_TYPE:
instrSet = 'RV' + xlen + instrType
print('Generating Assembly for {}'.format(instrSet))
dut = TestGen(numInstr=NUMINSTR, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH)
# regFile =
dut.model.memory.populateMemory(memDict = memInit)
dut.exportASM(instrSet = instrSet, instrTypes = instrType)
print('Generating {} Assembly Instructions for {}'.format(num_instructions, instrSet))
dut = TestGen(numInstr=num_instructions, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH)
# regFile =
dut.model.memory.populateMemory(memDict = memInit)
dut.exportASM(instrSet = instrSet, instrTypes = instrType)