From 968994c04a3f97e50ccc196f94e9382273d03978 Mon Sep 17 00:00:00 2001 From: Shriya Nadgauda Date: Mon, 3 May 2021 22:07:36 -0400 Subject: [PATCH] updated pipeline tests --- wally-pipelined/config/rv32ic/wally-config.vh | 2 +- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- .../testbench/testbench-imperas.sv | 37 ++- wally-pipelined/testgen/testgen-PIPELINE.py | 297 ++++++++++++++---- 4 files changed, 259 insertions(+), 79 deletions(-) diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index fa16fdb8..0d5d0bf7 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -69,7 +69,7 @@ `define BOOTTIMBASE 32'h00000000 `define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0007FFFF +`define TIMRANGE 32'h0FFFFFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 3ef92055..78653f89 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIMBASE 32'h00000000 `define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0007FFFF +`define TIMRANGE 32'h0FFFFFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index f7a77b6b..aeb0a9e8 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -34,9 +34,11 @@ module testbench(); logic clk; logic reset; + parameter SIGNATURESIZE = 5000000; + int test, i, errors, totalerrors; - logic [31:0] sig32[0:10000]; - logic [`XLEN-1:0] signature[0:10000]; + logic [31:0] sig32[0:SIGNATURESIZE]; + logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; @@ -115,6 +117,7 @@ module testbench(); }; string tests64i[] = '{ + "rv64i/WALLY-PIPELINE-100K", "f7ff0", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", "rv64i/I-ADDIW-01", "3000", @@ -260,6 +263,7 @@ module testbench(); }; string tests32i[] = { + "rv32i/WALLY-PIPELINE-100K", "10a800", "rv32i/I-ADD-01", "2000", "rv32i/I-ADDI-01","2000", "rv32i/I-AND-01","2000", @@ -275,7 +279,7 @@ module testbench(); "rv32i/I-EBREAK-01","2000", "rv32i/I-ECALL-01","2000", "rv32i/I-ENDIANESS-01","2010", - "rv32i/I-IO-01","2030", + "rv32i/I-IO-01","2030rv", "rv32i/I-JAL-01","3000", "rv32i/I-JALR-01","3000", "rv32i/I-LB-01","3020", @@ -334,8 +338,7 @@ module testbench(); "rv32i/WALLY-CSRRC", "4000", "rv32i/WALLY-CSRRWI", "3000", "rv32i/WALLY-CSRRSI", "3000", - "rv32i/WALLY-CSRRCI", "3000", - "rv32i/WALLY-PIPELINE", "1a800" + "rv32i/WALLY-CSRRCI", "3000" }; string testsBP64[] = '{ @@ -358,16 +361,16 @@ module testbench(); }; string tests32p[] = '{ - "rv32p/WALLY-MCAUSE", "2000", - "rv32p/WALLY-SCAUSE", "2000", - "rv32p/WALLY-MEPC", "5000", - "rv32p/WALLY-SEPC", "4000", - "rv32p/WALLY-MTVAL", "5000", - "rv32p/WALLY-STVAL", "4000", - "rv32p/WALLY-MARCHID", "4000", - "rv32p/WALLY-MIMPID", "4000", - "rv32p/WALLY-MHARTID", "4000", - "rv32p/WALLY-MVENDORID", "4000" + // "rv32p/WALLY-MCAUSE", "2000", + // "rv32p/WALLY-SCAUSE", "2000", + // "rv32p/WALLY-MEPC", "5000", + // "rv32p/WALLY-SEPC", "4000", + // "rv32p/WALLY-MTVAL", "5000", + // "rv32p/WALLY-STVAL", "4000", + // "rv32p/WALLY-MARCHID", "4000", + // "rv32p/WALLY-MIMPID", "4000", + // "rv32p/WALLY-MHARTID", "4000", + // "rv32p/WALLY-MVENDORID", "4000" }; string tests64periph[] = '{ @@ -499,7 +502,7 @@ module testbench(); $display("Code ended with ecall with gp = 1"); #60; // give time for instructions in pipeline to finish // clear signature to prevent contamination from previous tests - for(i=0; i<10000; i=i+1) begin + for(i=0; i 0: + newValueBin = bin(newValue)[2:] + elif newValue == 0: + newValueBin = "0" * model.xlen + else: + newValueBin = bin(newValue)[3:] + newValueBinTrunk = newValueBin[-model.xlen:] + rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) + model.pc += 4 + return 'addiw {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) + + @classmethod + def Instr_slliw(self, model, rd = None, rs1 = None, imm = None): + bits = rs1.bits + immBits = imm.bits[-5:] + immShift = int(immBits, 2) + shifted = bits[-(len(bits) - immShift):] + shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted))) + rd.setValue(newValue = shiftedExt, signed = 1) + model.pc += 4 + return 'slliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) + + @classmethod + def Instr_srliw(self, model, rd = None, rs1 = None, imm = None): + bits = rs1.bits + immBits = imm.bits[-5:] + immShift = int(immBits, 2) + shifted = bits[0:len(bits) - immShift] + extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen) + rd.setBits(newBits = extShifted, signed = 1) + model.pc += 4 + return 'srliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) + + @classmethod + def Instr_sraiw(self, model, rd = None, rs1 = None, imm = None): + bits = rs1.bits + immBits = imm.bits[-5:] + immShift = int(immBits, 2) + shifted = bits[0:len(bits) - immShift] + extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen) + rd.setBits(newBits = extShifted, signed = 1) + model.pc += 4 + return 'sraiw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) + + @classmethod + def Instr_Sd(self, model, rs1 = None, rs2 = None, imm = None): + addr = imm.getDecValue() + model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD) + model.pc += 4 + return 'Sd {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName()) + + @classmethod + def Instr_addw(self, model, rd = None, rs1 = None, rs2 = None): + newValue = rs1.getDecValue() + rs2.getDecValue() + newValueBin = 0 + if newValue > 0: + newValueBin = bin(newValue)[2:] + elif newValue == 0: + newValueBin = "0" * model.xlen + else: + newValueBin = bin(newValue)[3:] + newValueBinTrunk = newValueBin[-model.xlen:] + rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) + model.pc += 4 + return 'addw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + @classmethod + def Instr_subw(self, model, rd = None, rs1 = None, rs2 = None): + newValue = rs1.getDecValue() - rs2.getDecValue() + newValueBin = 0 + if newValue > 0: + newValueBin = bin(newValue)[2:] + elif newValue == 0: + newValueBin = "0" * model.xlen + else: + newValueBin = bin(newValue)[3:] + newValueBinTrunk = newValueBin[-model.xlen:] + rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) + model.pc += 4 + return 'subw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + @classmethod + def Instr_sllw(self, model, rd = None, rs1 = None, rs2 = None): + bits = rs1.bits + rs2Bin = rs2.bits[-5:] + rs2Shift = int(rs2Bin,2) + shifted = bits[-(len(bits) - rs2Shift):] + shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted))) + rd.setValue(newValue = shiftedExt, signed = 1) + model.pc += 4 + return 'sllw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + @classmethod + def Instr_srlw(self, model, rd = None, rs1 = None, rs2 = None): + bits = rs1.bits + rs2Bin = rs2.bits[-5:] + rs2Shift = int(rs2Bin,2) + shifted = bits[0:len(bits) - rs2Shift] + extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen) + rd.setBits(newBits = extShifted, signed = 1) + model.pc += 4 + return 'srlw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + @classmethod + def Instr_sraw(self, model, rd = None, rs1 = None, rs2 = None): + bits = rs1.bits + rs2Bin = rs2.bits[-5:] + rs2Shift = int(rs2Bin,2) + shifted = bits[0:len(bits) - rs2Shift] + extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen) + rd.setBits(newBits = extShifted, signed = 1) + model.pc += 4 + return 'sraw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + ################################################################################################### # Global Constants ################################################################################################### @@ -1693,7 +1870,7 @@ GRANULARITY = Enum('granularity', ['WORD', 'HALFWORD', 'BYTE']) INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \ 'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \ 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \ - 'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal'], \ + 'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal', 'jalr'], \ 'RV64I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \ 'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \ 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \ @@ -1703,9 +1880,11 @@ INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', } -InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and'], \ - 'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr'], \ - 'S' : ['sw', 'sh', 'sb'], \ +InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', \ + 'addw', 'subw', 'sllw', 'srlw', 'sraw'], \ + 'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr', \ + 'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw'], \ + 'S' : ['sw', 'sh', 'sb', 'Sd'], \ 'B' : ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu'], \ 'U' : ['lui', 'auipc'], \ 'J' : ['jal'], \ @@ -1714,27 +1893,25 @@ InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', # Main Body ################################################################################################### -XLEN = ['32'] +XLEN = ['32', '64'] INSTRUCTION_TYPE = ['I'] -NUMINSTR = 70000 +NUMINSTR = [100000, 1000000] IMPERASPATH = "../../imperas-riscv-tests/riscv-test-suite/" seed(42) np.random.seed(42) -for xlen in XLEN: - memInit = {} - for i in range(0, 400, 4): - val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1) - memInit[i] = val - for instrType in INSTRUCTION_TYPE: - instrSet = 'RV' + xlen + instrType - - print('Generating Assembly for {}'.format(instrSet)) - - dut = TestGen(numInstr=NUMINSTR, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH) - # regFile = - dut.model.memory.populateMemory(memDict = memInit) - dut.exportASM(instrSet = instrSet, instrTypes = instrType) - - +for num_instructions in NUMINSTR: + for xlen in XLEN: + memInit = {} + for i in range(0, 400, 4): + val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1) + memInit[i] = val + for instrType in INSTRUCTION_TYPE: + instrSet = 'RV' + xlen + instrType + print('Generating {} Assembly Instructions for {}'.format(num_instructions, instrSet)) + + dut = TestGen(numInstr=num_instructions, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH) + # regFile = + dut.model.memory.populateMemory(memDict = memInit) + dut.exportASM(instrSet = instrSet, instrTypes = instrType) \ No newline at end of file