Fixed bug in the top level of fpga verilog.

2021-12-03 17:55:36 -06:00 · 2021-12-03 17:55:36 -06:00 · 955ddcfbe1
commit 955ddcfbe1
parent 5b4ff4526e
1 changed files with 0 additions and 1 deletions
--- a/fpga/src/fpgaTop.v
+++ b/fpga/src/fpgaTop.v
@ -44,7 +44,6 @@ module fpgaTop

   output 	   calib,
   output 	   cpu_reset,
-   output 	   ddr4_sdram_c1_062,
   output 	   ahblite_resetn,

   output [16 : 0] c0_ddr4_adr,