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Fixed bug in the top level of fpga verilog.

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Ross Thompson 2021-12-03 17:55:36 -06:00
parent 5b4ff4526e
commit 955ddcfbe1
1 changed files with 0 additions and 1 deletions
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fpga/src/fpgaTop.v
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@ -44,7 +44,6 @@ module fpgaTop
output calib, output calib,
output cpu_reset, output cpu_reset,
output ddr4_sdram_c1_062,
output ahblite_resetn, output ahblite_resetn,
output [16 : 0] c0_ddr4_adr, output [16 : 0] c0_ddr4_adr,