Restructured negateintres to avoid lint error, but one still shows on shiftcorrection

pipelined/src/fpu/postproc/negateintres.sv

@@ -37,10 +37,12 @@ module negateintres(
   output logic [`XLEN+1:0]        CvtNegRes       // possibly negated integer result
 );
 
+  logic [`XLEN+1:0]               CvtPreRes;      // integer result with rounding
   logic [2:0]                     CvtNegResMsbs3; // first three msbs of possibly negated result
     
   // round and negate the positive res if needed
-    assign CvtNegRes = Xs ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
+  assign CvtPreRes =  {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
+  mux2 #(`XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
     
   // select 2 most significant bits
   mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);

pipelined/src/privileged/privileged.sv

@@ -51,10 +51,11 @@ module privileged (
   input  logic             ICacheMiss,
   input  logic             ICacheAccess,
   input  logic             PrivilegedM,
-  input  logic             InstrPageFaultF, HPTWInstrAccessFaultM, LoadPageFaultM, StoreAmoPageFaultM,
-  input  logic             InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrM,
-  input  logic             LoadMisalignedFaultM,
-  input  logic             StoreAmoMisalignedFaultM,
+  input  logic             HPTWInstrAccessFaultM, 
+  input  logic             InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
+  input  logic             InstrMisalignedFaultM, 
+  input  logic             LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
+  input  logic             IllegalIEUInstrFaultD, IllegalFPUInstrM,
   input  logic             MTimerInt, MExtInt, SExtInt, MSwInt,
   input  logic [63:0]      MTIME_CLINT, 
   input  logic [`XLEN-1:0] IEUAdrM,