From 93233fbb456f992714769e8c8ba32c554306e44a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 12 Jan 2023 07:28:52 -0800
Subject: [PATCH] Restructured negateintres to avoid lint error, but one still
 shows on shiftcorrection

---
 pipelined/src/fpu/postproc/negateintres.sv | 28 ++++++++++++----------
 pipelined/src/privileged/privileged.sv     | 17 ++++++-------
 2 files changed, 24 insertions(+), 21 deletions(-)

diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv
index 5b7e7cbf..939bcc33 100644
--- a/pipelined/src/fpu/postproc/negateintres.sv
+++ b/pipelined/src/fpu/postproc/negateintres.sv
@@ -28,21 +28,23 @@
 `include "wally-config.vh"
 
 module negateintres(
-    input  logic                    Signed,         // is the integer input signed
-    input  logic                    Int64,          // is the integer input 64-bits
-    input  logic                    Plus1,          // should one be added for rounding?
-    input  logic                    Xs,             // X sign
-    input  logic [`NORMSHIFTSZ-1:0] Shifted,        // output from normalization shifter
-    output logic [1:0]              CvtNegResMsbs,  // most signigficant bits of possibly negated result
-    output logic [`XLEN+1:0]        CvtNegRes       // possibly negated integer result
+  input  logic                    Signed,         // is the integer input signed
+  input  logic                    Int64,          // is the integer input 64-bits
+  input  logic                    Plus1,          // should one be added for rounding?
+  input  logic                    Xs,             // X sign
+  input  logic [`NORMSHIFTSZ-1:0] Shifted,        // output from normalization shifter
+  output logic [1:0]              CvtNegResMsbs,  // most signigficant bits of possibly negated result
+  output logic [`XLEN+1:0]        CvtNegRes       // possibly negated integer result
 );
 
-    logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result
+  logic [`XLEN+1:0]               CvtPreRes;      // integer result with rounding
+  logic [2:0]                     CvtNegResMsbs3; // first three msbs of possibly negated result
     
-    // round and negate the positive res if needed
-    assign CvtNegRes = Xs ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
+  // round and negate the positive res if needed
+  assign CvtPreRes =  {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
+  mux2 #(`XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
     
-    // select 2 most significant bits
-    mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);
-    mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegResMsbs3[1:0], Signed, CvtNegResMsbs);
+  // select 2 most significant bits
+  mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);
+  mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegResMsbs3[1:0], Signed, CvtNegResMsbs);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 73ecfada..0acc8c15 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -41,20 +41,21 @@ module privileged (
   output logic             sfencevmaM,
   input  logic             InstrValidM, CommittedM, CommittedF, 
   input  logic             FRegWriteM, LoadStallD,
-  input  logic 		   DirPredictionWrongM,
-  input  logic 		   BTBPredPCWrongM,
-  input  logic 		   RASPredPCWrongM,
-  input  logic 		   PredictionInstrClassWrongM,
+  input  logic 		         DirPredictionWrongM,
+  input  logic 		         BTBPredPCWrongM,
+  input  logic 		         RASPredPCWrongM,
+  input  logic 		          PredictionInstrClassWrongM,
   input  logic [4:0]       InstrClassM,
   input  logic             DCacheMiss,
   input  logic             DCacheAccess,
   input  logic             ICacheMiss,
   input  logic             ICacheAccess,
   input  logic             PrivilegedM,
-  input  logic             InstrPageFaultF, HPTWInstrAccessFaultM, LoadPageFaultM, StoreAmoPageFaultM,
-  input  logic             InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrM,
-  input  logic             LoadMisalignedFaultM,
-  input  logic             StoreAmoMisalignedFaultM,
+  input  logic             HPTWInstrAccessFaultM, 
+  input  logic             InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
+  input  logic             InstrMisalignedFaultM, 
+  input  logic             LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
+  input  logic             IllegalIEUInstrFaultD, IllegalFPUInstrM,
   input  logic             MTimerInt, MExtInt, SExtInt, MSwInt,
   input  logic [63:0]      MTIME_CLINT, 
   input  logic [`XLEN-1:0] IEUAdrM,