Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Restructured negateintres to avoid lint error, but one still shows on shiftcorrection

Browse Source
This commit is contained in:
David Harris 2023-01-12 07:28:52 -08:00
parent 1ad6ac1393
commit 93233fbb45
2 changed files with 24 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
pipelined/src/fpu/postproc/negateintres.sv
View File

@ -28,21 +28,23 @@
`include "wally-config.vh" `include "wally-config.vh"
module negateintres( module negateintres(
input logic Signed, // is the integer input signed input logic Signed, // is the integer input signed
input logic Int64, // is the integer input 64-bits input logic Int64, // is the integer input 64-bits
input logic Plus1, // should one be added for rounding? input logic Plus1, // should one be added for rounding?
input logic Xs, // X sign input logic Xs, // X sign
input logic [`NORMSHIFTSZ-1:0] Shifted, // output from normalization shifter input logic [`NORMSHIFTSZ-1:0] Shifted, // output from normalization shifter
output logic [1:0] CvtNegResMsbs, // most signigficant bits of possibly negated result output logic [1:0] CvtNegResMsbs, // most signigficant bits of possibly negated result
output logic [`XLEN+1:0] CvtNegRes // possibly negated integer result output logic [`XLEN+1:0] CvtNegRes // possibly negated integer result
); );
logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result logic [`XLEN+1:0] CvtPreRes; // integer result with rounding
logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result
// round and negate the positive res if needed // round and negate the positive res if needed
assign CvtNegRes = Xs ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}; assign CvtPreRes = {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
mux2 #(`XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
// select 2 most significant bits // select 2 most significant bits
mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3); mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);
mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegResMsbs3[1:0], Signed, CvtNegResMsbs); mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegResMsbs3[1:0], Signed, CvtNegResMsbs);
endmodule endmodule

17
pipelined/src/privileged/privileged.sv
View File

@ -41,20 +41,21 @@ module privileged (
output logic sfencevmaM, output logic sfencevmaM,
input logic InstrValidM, CommittedM, CommittedF, input logic InstrValidM, CommittedM, CommittedF,
input logic FRegWriteM, LoadStallD, input logic FRegWriteM, LoadStallD,
input logic DirPredictionWrongM, input logic DirPredictionWrongM,
input logic BTBPredPCWrongM, input logic BTBPredPCWrongM,
input logic RASPredPCWrongM, input logic RASPredPCWrongM,
input logic PredictionInstrClassWrongM, input logic PredictionInstrClassWrongM,
input logic [4:0] InstrClassM, input logic [4:0] InstrClassM,
input logic DCacheMiss, input logic DCacheMiss,
input logic DCacheAccess, input logic DCacheAccess,
input logic ICacheMiss, input logic ICacheMiss,
input logic ICacheAccess, input logic ICacheAccess,
input logic PrivilegedM, input logic PrivilegedM,
input logic InstrPageFaultF, HPTWInstrAccessFaultM, LoadPageFaultM, StoreAmoPageFaultM, input logic HPTWInstrAccessFaultM,
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrM, input logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
input logic LoadMisalignedFaultM, input logic InstrMisalignedFaultM,
input logic StoreAmoMisalignedFaultM, input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
input logic IllegalIEUInstrFaultD, IllegalFPUInstrM,
input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
input logic [`XLEN-1:0] IEUAdrM, input logic [`XLEN-1:0] IEUAdrM,