Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

generic cleanup

Browse Source
This commit is contained in:
David Harris 2023-01-14 19:02:38 -08:00
parent 9c79078be1
commit 91afe5522b
4 changed files with 43 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
pipelined/src/ebu/ahbcacheinterface.sv
View File

@ -30,10 +30,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) (
(
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
// bus interface // bus interface
input logic HREADY, input logic HREADY,
input logic [`AHBW-1:0] HRDATA, input logic [`AHBW-1:0] HRDATA,
@ -64,7 +62,8 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
input logic [2:0] Funct3, input logic [2:0] Funct3,
output logic SelBusBeat, output logic SelBusBeat,
output logic BusStall, output logic BusStall,
output logic BusCommitted); output logic BusCommitted
);
localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu. localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu.
@ -75,6 +74,8 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE
logic [`AHBW-1:0] PreHWDATA; logic [`AHBW-1:0] PreHWDATA;
genvar index; genvar index;
// fetch buffer is made of BEATSPERLINE flip-flops
for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
logic [BEATSPERLINE-1:0] CaptureBeat; logic [BEATSPERLINE-1:0] CaptureBeat;
assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);

1
pipelined/src/generic/mux.sv
View File

@ -27,7 +27,6 @@
`include "wally-config.vh" `include "wally-config.vh"
/* verilator lint_off DECLFILENAME */ /* verilator lint_off DECLFILENAME */
module mux2 #(parameter WIDTH = 8) ( module mux2 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, input logic [WIDTH-1:0] d0, d1,
input logic s, input logic s,

1
pipelined/src/generic/priorityonehot.sv
View File

@ -41,6 +41,7 @@ module priorityonehot #(parameter N = 8) (
); );
genvar i; genvar i;
assign y[0] = a[0]; assign y[0] = a[0];
for (i=1; i<N; i++) begin:poh for (i=1; i<N; i++) begin:poh
assign y[i] = a[i] & ~|a[i-1:0]; assign y[i] = a[i] & ~|a[i-1:0];

5
pipelined/src/generic/prioritythermometer.sv
View File

@ -31,8 +31,6 @@
`include "wally-config.vh" `include "wally-config.vh"
/* verilator lint_off UNOPTFLAT */
module prioritythermometer #(parameter N = 8) ( module prioritythermometer #(parameter N = 8) (
input logic [N-1:0] a, input logic [N-1:0] a,
output logic [N-1:0] y output logic [N-1:0] y
@ -42,13 +40,14 @@ module prioritythermometer #(parameter N = 8) (
// Rather than linear. // Rather than linear.
// create thermometer code mask // create thermometer code mask
/* verilator lint_off UNOPTFLAT */
genvar i; genvar i;
assign y[0] = ~a[0]; assign y[0] = ~a[0];
for (i=1; i<N; i++) begin:therm for (i=1; i<N; i++) begin:therm
assign y[i] = y[i-1] & ~a[i]; assign y[i] = y[i-1] & ~a[i];
end end
/* verilator lint_on UNOPTFLAT */
endmodule endmodule
/* verilator lint_on UNOPTFLAT */