From 91afe5522b64740ce3a98c0df10a69aa51f208ee Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 14 Jan 2023 19:02:38 -0800
Subject: [PATCH] generic cleanup

---
 pipelined/src/ebu/ahbcacheinterface.sv       | 75 ++++++++++----------
 pipelined/src/generic/mux.sv                 |  1 -
 pipelined/src/generic/priorityonehot.sv      |  1 +
 pipelined/src/generic/prioritythermometer.sv |  9 ++-
 4 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv
index e3d84547..f746a60e 100644
--- a/pipelined/src/ebu/ahbcacheinterface.sv
+++ b/pipelined/src/ebu/ahbcacheinterface.sv
@@ -30,51 +30,52 @@
 
 `include "wally-config.vh"
 
-module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
-  (
-  input logic                 HCLK, HRESETn,
-  
+module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) (
+  input  logic                 HCLK, HRESETn,
   // bus interface
-  input logic                 HREADY,
-  input logic [`AHBW-1:0]     HRDATA,
-  output logic [2:0]          HSIZE,
-  output logic [2:0]          HBURST,
-  output logic [1:0]          HTRANS,
-  output logic                HWRITE,
-  output logic [`PA_BITS-1:0] HADDR,
-  output logic [`AHBW-1:0]    HWDATA,
-  output logic [`AHBW/8-1:0]  HWSTRB,
-  output logic [LOGWPL-1:0]   BeatCount,
+  input  logic                 HREADY,
+  input  logic [`AHBW-1:0]     HRDATA,
+  output logic [2:0]           HSIZE,
+  output logic [2:0]           HBURST,
+  output logic [1:0]           HTRANS,
+  output logic                 HWRITE,
+  output logic [`PA_BITS-1:0]  HADDR,
+  output logic [`AHBW-1:0]     HWDATA,
+  output logic [`AHBW/8-1:0]   HWSTRB,
+  output logic [LOGWPL-1:0]    BeatCount,
   
   // cache interface
-  input logic [`PA_BITS-1:0]  CacheBusAdr,
-  input logic [`LLEN-1:0]     CacheReadDataWordM,
-  input logic [`LLEN-1:0]     WriteDataM,
-  input logic                 CacheableOrFlushCacheM,
-  input logic [1:0]           CacheBusRW,
-  output logic                CacheBusAck,
-  output logic [LINELEN-1:0]  FetchBuffer, 
-  input logic                 Cacheable,
+  input  logic [`PA_BITS-1:0]  CacheBusAdr,
+  input  logic [`LLEN-1:0]     CacheReadDataWordM,
+  input  logic [`LLEN-1:0]     WriteDataM,
+  input  logic                 CacheableOrFlushCacheM,
+  input  logic [1:0]           CacheBusRW,
+  output logic                 CacheBusAck,
+  output logic [LINELEN-1:0]   FetchBuffer, 
+  input  logic                 Cacheable,
  
   // lsu/ifu interface
-  input logic                 Flush,
-  input logic [`PA_BITS-1:0]  PAdr,
-  input logic [1:0]           BusRW,
-  input logic                 Stall,
-  input logic [2:0]           Funct3,
-  output logic                SelBusBeat,
-  output logic                BusStall,
-  output logic                BusCommitted);
+  input  logic                 Flush,
+  input  logic [`PA_BITS-1:0]  PAdr,
+  input  logic [1:0]           BusRW,
+  input  logic                 Stall,
+  input  logic [2:0]           Funct3,
+  output logic                 SelBusBeat,
+  output logic                 BusStall,
+  output logic                 BusCommitted
+);
   
-  localparam integer          LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu.
+  localparam integer           LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu.
 
-  localparam integer   BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0;
-  logic [`PA_BITS-1:0] LocalHADDR;
-  logic [LOGWPL-1:0]   BeatCountDelayed;
-  logic                CaptureEn;
-  logic [`AHBW-1:0]    PreHWDATA;
+  localparam integer           BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0;
+  logic [`PA_BITS-1:0]         LocalHADDR;
+  logic [LOGWPL-1:0]           BeatCountDelayed;
+  logic                        CaptureEn;
+  logic [`AHBW-1:0]            PreHWDATA;
 
-  genvar                      index;
+  genvar                       index;
+
+  // fetch buffer is made of BEATSPERLINE flip-flops
   for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
     logic [BEATSPERLINE-1:0] CaptureBeat;
     assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
diff --git a/pipelined/src/generic/mux.sv b/pipelined/src/generic/mux.sv
index c3f0e5f9..636c19c9 100644
--- a/pipelined/src/generic/mux.sv
+++ b/pipelined/src/generic/mux.sv
@@ -27,7 +27,6 @@
 `include "wally-config.vh"
 /* verilator lint_off DECLFILENAME */
 
-
 module mux2 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] d0, d1, 
   input  logic             s, 
diff --git a/pipelined/src/generic/priorityonehot.sv b/pipelined/src/generic/priorityonehot.sv
index 51c155c1..ba5ebb90 100644
--- a/pipelined/src/generic/priorityonehot.sv
+++ b/pipelined/src/generic/priorityonehot.sv
@@ -41,6 +41,7 @@ module priorityonehot #(parameter N = 8) (
 );
 
   genvar i;
+  
   assign y[0] = a[0];
   for (i=1; i<N; i++) begin:poh
     assign y[i] = a[i] & ~|a[i-1:0];
diff --git a/pipelined/src/generic/prioritythermometer.sv b/pipelined/src/generic/prioritythermometer.sv
index 3054298a..d1970a80 100644
--- a/pipelined/src/generic/prioritythermometer.sv
+++ b/pipelined/src/generic/prioritythermometer.sv
@@ -31,24 +31,23 @@
 
 `include "wally-config.vh"
 
-/* verilator lint_off UNOPTFLAT */
-
 module prioritythermometer #(parameter N = 8) (
   input  logic  [N-1:0] a,
   output logic  [N-1:0] y
 );
 
-// Carefully crafted so design compiler will synthesize into a fast tree structure
-//  Rather than linear.
+  // Carefully crafted so design compiler will synthesize into a fast tree structure
+  //  Rather than linear.
 
   // create thermometer code mask
+  /* verilator lint_off UNOPTFLAT */
   genvar i;
   assign y[0] = ~a[0];
   for (i=1; i<N; i++) begin:therm
     assign y[i] = y[i-1] & ~a[i];
   end
+  /* verilator lint_on UNOPTFLAT */
 endmodule
 
 
-/* verilator lint_on UNOPTFLAT */