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Unified on-the-fly conversion working for radix 2; broke radix-4 division

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This commit is contained in:
David Harris 2022-09-19 00:04:00 -07:00
parent 9fb3382ec3
commit 91194a9c3e
4 changed files with 24 additions and 6 deletions
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3
pipelined/src/fpu/fdivsqrtfsm.sv
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@ -55,7 +55,8 @@ module fdivsqrtfsm(
logic SpecialCase; logic SpecialCase;
logic [`DURLEN-1:0] cycles; logic [`DURLEN-1:0] cycles;
assign EarlyTermShiftE = step; assign EarlyTermShiftE = 0; // *** remove this signal when having unified design
// assign EarlyTermShiftE = step;
// terminate immediately on special cases // terminate immediately on special cases
assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);

20
pipelined/src/fpu/fdivsqrtiter.sv
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@ -80,7 +80,9 @@ module fdivsqrtiter(
logic [`DIVb:0] QMMux; logic [`DIVb:0] QMMux;
logic [`DIVb+1:0] NextC; logic [`DIVb+1:0] NextC;
logic [`DIVb+1:0] CMux; logic [`DIVb+1:0] CMux;
logic [`DIVb:0] SMux; logic [`DIVb:0] SMux, SMMux;
logic [`DIVb:0] initS, initSM;
// Top Muxes and Registers // Top Muxes and Registers
// When start is asserted, the inputs are loaded into the divider. // When start is asserted, the inputs are loaded into the divider.
@ -163,9 +165,21 @@ module fdivsqrtiter(
flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]); flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]);
// if starting new square root, set S to 1 and SM to 0 // if starting new square root, set S to 1 and SM to 0
flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]); /* flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]);
mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux); mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux);
flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]); flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]);
flopenr #(`DIVb+1) Sreg(clk, DivStart, DivBusy, SNext[`DIVCOPIES-1], S[0]);
mux2 #(`DIVb+1) SMMmux(SMNext[`DIVCOPIES-1], '1, DivStart, SMux);
flopen #(`DIVb+1) SMreg(clk, DivStart|DivBusy, SMux, SM[0]);*/
// Initialize S to 1 and SM to 0 for square root; S to 0 and SM to -1 for division
assign initS = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0;
assign initSM = SqrtE ? 0 : '1;
mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], initS, DivStart, SMux);
mux2 #(`DIVb+1) SMmux(SMNext[`DIVCOPIES-1], initSM, DivStart, SMMux);
flopen #(`DIVb+1) SReg(clk, DivStart|DivBusy, SMux, S[0]);
flopen #(`DIVb+1) SMReg(clk, DivStart|DivBusy, SMMux, SM[0]);
assign FirstWS = WS[0]; assign FirstWS = WS[0];
assign FirstWC = WC[0]; assign FirstWC = WC[0];

6
pipelined/src/fpu/fdivsqrtpostproc.sv
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@ -75,7 +75,9 @@ module fdivsqrtpostproc(
if(NegSticky) QmM = {FirstSM[`DIVb-1-(`RADIX/4):0], 1'b0}; if(NegSticky) QmM = {FirstSM[`DIVb-1-(`RADIX/4):0], 1'b0};
else QmM = {FirstS[`DIVb-1-(`RADIX/4):0], 1'b0}; else QmM = {FirstS[`DIVb-1-(`RADIX/4):0], 1'b0};
else else
if(NegSticky) QmM = FirstQM[`DIVb-(`RADIX/4):0]; if(NegSticky) QmM = FirstSM[`DIVb-(`RADIX/4):0];
else QmM = FirstQ[`DIVb-(`RADIX/4):0]; else QmM = FirstS[`DIVb-(`RADIX/4):0];
//if(NegSticky) QmM = FirstQM[`DIVb-(`RADIX/4):0];
//else QmM = FirstQ[`DIVb-(`RADIX/4):0];
endmodule endmodule

1
pipelined/src/fpu/otfc.sv
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@ -73,6 +73,7 @@ module sotfc2(
logic [`DIVb:0] CExt; logic [`DIVb:0] CExt;
assign CExt = C[`DIVb:0]; // {1'b1, C[`DIVb-1:0]}; assign CExt = C[`DIVb:0]; // {1'b1, C[`DIVb-1:0]};
// *** define K and use it; show in textbook
always_comb begin always_comb begin
if (sp) begin if (sp) begin