From 91194a9c3e767d841259d88ff56f8c2cdc9b8043 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 19 Sep 2022 00:04:00 -0700
Subject: [PATCH] Unified on-the-fly conversion working for radix 2; broke
 radix-4 division

---
 pipelined/src/fpu/fdivsqrtfsm.sv      |  3 ++-
 pipelined/src/fpu/fdivsqrtiter.sv     | 20 +++++++++++++++++---
 pipelined/src/fpu/fdivsqrtpostproc.sv |  6 ++++--
 pipelined/src/fpu/otfc.sv             |  1 +
 4 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv
index 29666b9f..c4715886 100644
--- a/pipelined/src/fpu/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrtfsm.sv
@@ -55,7 +55,8 @@ module fdivsqrtfsm(
   logic SpecialCase;
   logic [`DURLEN-1:0] cycles;
 
-  assign EarlyTermShiftE = step;
+  assign EarlyTermShiftE = 0; // *** remove this signal when having unified design
+//  assign EarlyTermShiftE = step; 
 
   // terminate immediately on special cases
   assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
diff --git a/pipelined/src/fpu/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrtiter.sv
index 861f4950..25bbdbb5 100644
--- a/pipelined/src/fpu/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrtiter.sv
@@ -80,7 +80,9 @@ module fdivsqrtiter(
   logic [`DIVb:0] QMMux;
   logic [`DIVb+1:0] NextC;
   logic [`DIVb+1:0] CMux;
-  logic [`DIVb:0] SMux;
+  logic [`DIVb:0] SMux, SMMux;
+  logic [`DIVb:0] initS, initSM;
+
 
   // Top Muxes and Registers
   // When start is asserted, the inputs are loaded into the divider.
@@ -163,9 +165,21 @@ module fdivsqrtiter(
   flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]);
 
   // if starting new square root, set S to 1 and SM to 0
-  flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]);
+/*  flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]);
   mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux);
-  flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]);
+  flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]); 
+  flopenr #(`DIVb+1) Sreg(clk, DivStart, DivBusy, SNext[`DIVCOPIES-1], S[0]);
+  mux2 #(`DIVb+1) SMMmux(SMNext[`DIVCOPIES-1], '1, DivStart, SMux);
+  flopen #(`DIVb+1) SMreg(clk, DivStart|DivBusy, SMux, SM[0]);*/
+
+  // Initialize S to 1 and SM to 0 for square root; S to 0 and SM to -1 for division
+  assign initS = SqrtE ? {1'b1, {(`DIVb){1'b0}}} : 0;
+  assign initSM = SqrtE ? 0 : '1; 
+  mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], initS, DivStart, SMux);
+  mux2 #(`DIVb+1) SMmux(SMNext[`DIVCOPIES-1], initSM, DivStart, SMMux);
+  flopen #(`DIVb+1) SReg(clk, DivStart|DivBusy, SMux, S[0]);
+  flopen #(`DIVb+1) SMReg(clk, DivStart|DivBusy, SMMux, SM[0]);
+  
 
   assign FirstWS = WS[0];
   assign FirstWC = WC[0];
diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv
index 1f2ee6cb..1b709a32 100644
--- a/pipelined/src/fpu/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpostproc.sv
@@ -75,7 +75,9 @@ module fdivsqrtpostproc(
       if(NegSticky) QmM = {FirstSM[`DIVb-1-(`RADIX/4):0], 1'b0};
       else          QmM = {FirstS[`DIVb-1-(`RADIX/4):0], 1'b0};
     else  
-      if(NegSticky) QmM = FirstQM[`DIVb-(`RADIX/4):0];
-      else          QmM = FirstQ[`DIVb-(`RADIX/4):0];
+      if(NegSticky) QmM = FirstSM[`DIVb-(`RADIX/4):0];
+      else          QmM = FirstS[`DIVb-(`RADIX/4):0];
+      //if(NegSticky) QmM = FirstQM[`DIVb-(`RADIX/4):0];
+      //else          QmM = FirstQ[`DIVb-(`RADIX/4):0];
 
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/otfc.sv b/pipelined/src/fpu/otfc.sv
index 2b4d0f9c..042833de 100644
--- a/pipelined/src/fpu/otfc.sv
+++ b/pipelined/src/fpu/otfc.sv
@@ -73,6 +73,7 @@ module sotfc2(
   logic [`DIVb:0] CExt;
 
   assign CExt = C[`DIVb:0]; // {1'b1, C[`DIVb-1:0]};
+  // *** define K and use it; show in textbook
 
   always_comb begin
     if (sp) begin