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fdiv debug

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David Harris 2022-08-31 14:26:31 -07:00
parent 6912656aab
commit 8fad5073cd
1 changed files with 1 additions and 1 deletions
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pipelined/src/fpu/fdivsqrtstage4.sv
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@ -78,7 +78,7 @@ module fdivsqrtstage4 (
csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA); csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA);
otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext); sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C, .S, .SM, .SNext, .SMNext);
endmodule endmodule