From 8fad5073cd3f77cc3d2020c53701123e9d96d0ae Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 31 Aug 2022 14:26:31 -0700 Subject: [PATCH] fdiv debug --- pipelined/src/fpu/fdivsqrtstage4.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrtstage4.sv index 1865fe4a..02d99153 100644 --- a/pipelined/src/fpu/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrtstage4.sv @@ -78,7 +78,7 @@ module fdivsqrtstage4 ( csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA); otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); - sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext); + sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C, .S, .SM, .SNext, .SMNext); endmodule