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Working without dcache.

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This commit is contained in:
Ross Thompson 2021-12-30 16:01:31 -06:00
parent 91f67f19a7
commit 8e4467654a
2 changed files with 3 additions and 3 deletions
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2
wally-pipelined/config/rv32ic/wally-config.vh
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@ -50,7 +50,7 @@
`define UARCH_SUPERSCALR 0 `define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0 `define UARCH_SINGLECYCLE 0
`define MEM_DTIM 1 `define MEM_DTIM 1
`define MEM_DCACHE 1 `define MEM_DCACHE 0
`define MEM_IROM 1 `define MEM_IROM 1
`define MEM_ICACHE 1 `define MEM_ICACHE 1
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 0

4
wally-pipelined/src/lsu/busfsm.sv
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@ -27,7 +27,7 @@
module busfsm #(parameter integer WordCountThreshold, module busfsm #(parameter integer WordCountThreshold,
parameter integer LOGWPL, parameter integer CacheEnabled ) parameter integer LOGWPL, parameter logic CacheEnabled )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
@ -82,7 +82,7 @@ module busfsm #(parameter integer WordCountThreshold,
assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]); assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]);
assign CntEn = PreCntEn & LsuBusAck; assign CntEn = PreCntEn & LsuBusAck;
assign UnCachedAccess = ~CacheableM | ~CacheEnabled; assign UnCachedAccess = ~CacheEnabled | ~CacheableM;
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset) BusCurrState <= #1 STATE_BUS_READY; if (reset) BusCurrState <= #1 STATE_BUS_READY;