diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh
index e4e0bc48..ade57a71 100644
--- a/wally-pipelined/config/rv32ic/wally-config.vh
+++ b/wally-pipelined/config/rv32ic/wally-config.vh
@@ -50,7 +50,7 @@
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
 `define MEM_DTIM 1
-`define MEM_DCACHE 1
+`define MEM_DCACHE 0
 `define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 0
diff --git a/wally-pipelined/src/lsu/busfsm.sv b/wally-pipelined/src/lsu/busfsm.sv
index cdfe9b10..6f8a3921 100644
--- a/wally-pipelined/src/lsu/busfsm.sv
+++ b/wally-pipelined/src/lsu/busfsm.sv
@@ -27,7 +27,7 @@
 
 
 module busfsm #(parameter integer   WordCountThreshold,
-				parameter integer LOGWPL, parameter integer CacheEnabled )
+				parameter integer LOGWPL, parameter logic CacheEnabled )
   (input logic clk,
    input logic 				 reset,
 
@@ -82,7 +82,7 @@ module busfsm #(parameter integer   WordCountThreshold,
   assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]);
   assign CntEn = PreCntEn & LsuBusAck;
 
-  assign UnCachedAccess = ~CacheableM | ~CacheEnabled;
+  assign UnCachedAccess = ~CacheEnabled | ~CacheableM;
 
   always_ff @(posedge clk)
     if (reset)    BusCurrState <= #1 STATE_BUS_READY;