diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv
index 950b55ff..0106af7d 100644
--- a/pipelined/src/fpu/fma.sv
+++ b/pipelined/src/fpu/fma.sv
@@ -85,8 +85,8 @@ module fma(
         
     fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss);
 
-   
-    fmalza lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
+    
+    fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
 endmodule
 
 
diff --git a/pipelined/src/fpu/fmalza.sv b/pipelined/src/fpu/fmalza.sv
index 65fe9426..8e92a5dc 100644
--- a/pipelined/src/fpu/fmalza.sv
+++ b/pipelined/src/fpu/fmalza.sv
@@ -29,16 +29,14 @@
 
 `include "wally-config.vh"
 
-module fmalza( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
-    input logic [3*`NF+5:0] 	       A, // addend
+module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
+    input logic [WIDTH-1:0] 	       A, // addend
     input logic [2*`NF+3:0] 	       Pm, // product
     input logic 		       Cin, // carry in
     input logic sub,
-    output logic [$clog2(3*`NF+7)-1:0] SCnt   // normalization shift count for the positive result
+    output logic [$clog2(WIDTH+1)-1:0] SCnt   // normalization shift count for the positive result
     ); 
 
-    localparam WIDTH = 3*`NF+6;
-    
    logic [WIDTH:0] 	       F;
    logic [WIDTH-1:0]  B, P, G, K;
     logic [WIDTH-1:0] Pp1, Gm1, Km1;