forked from Github_Repos/cvw
small synthesis fixes
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@ -31,7 +31,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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package ahbliteState;
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package ahbliteState;
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typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
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typedef enum logic [3:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
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endpackage
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endpackage
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module ahblite (
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module ahblite (
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@ -30,7 +30,7 @@ module extend (
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input logic [2:0] ImmSrcD,
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input logic [2:0] ImmSrcD,
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output logic [`XLEN-1:0 ] ExtImmD);
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output logic [`XLEN-1:0 ] ExtImmD);
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logic [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
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localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
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generate
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generate
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always_comb
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always_comb
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@ -31,6 +31,7 @@ module decoder #(parameter BINARY_BITS = 3) (
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);
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);
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// *** Double check whether this synthesizes as expected
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// *** Double check whether this synthesizes as expected
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// -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists
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assign one_hot = 1 << binary;
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assign one_hot = 1 << binary;
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endmodule
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endmodule
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