small synthesis fixes

This commit is contained in:
bbracker 2021-05-04 15:21:01 -04:00
parent 8398e653dd
commit 8a7fc959eb
3 changed files with 3 additions and 2 deletions

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@ -31,7 +31,7 @@
`include "wally-config.vh" `include "wally-config.vh"
package ahbliteState; package ahbliteState;
typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype; typedef enum logic [3:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
endpackage endpackage
module ahblite ( module ahblite (

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@ -30,7 +30,7 @@ module extend (
input logic [2:0] ImmSrcD, input logic [2:0] ImmSrcD,
output logic [`XLEN-1:0 ] ExtImmD); output logic [`XLEN-1:0 ] ExtImmD);
logic [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
generate generate
always_comb always_comb

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@ -31,6 +31,7 @@ module decoder #(parameter BINARY_BITS = 3) (
); );
// *** Double check whether this synthesizes as expected // *** Double check whether this synthesizes as expected
// -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists
assign one_hot = 1 << binary; assign one_hot = 1 << binary;
endmodule endmodule